[ { num => 5, text => [ { col => undef, table => undef, text => "1.1" }, { col => undef, table => undef, text => "About this Manual" }, { col => undef, table => undef, text => "1.2" }, { col => undef, table => undef, text => "Nomenclature and Conventions" }, { col => undef, table => undef, text => "1.2.1" }, { col => undef, table => undef, text => "Numeric Representations" }, { col => undef, table => undef, text => "1.2.2" }, { col => undef, table => undef, text => "Register Description" }, { col => "heading", table => 0, text => "DST_HEIGHT_WIDTH_8 - W - 32 bits - [MMReg:0x158C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DST_WIDTH" }, { col => 1, table => 0, text => "23:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Destination Width Note: This is an initiator register. Y is incremented ", }, { col => 3, table => 0, text => "at end of blit. Write 15: 0 to E2_DST_X, Write 31: 16 to ", }, { col => 3, table => 0, text => "E2_DST_WIDTH, then signal blit_start. E2_DST_Y = E2_DEST_Y ", }, { col => 3, table => 0, text => "(+/-) E2_DST_HEIGHT as function of direction after blit is complete", }, { col => 0, table => 0, text => "DST_HEIGHT" }, { col => 1, table => 0, text => "31:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Destination Height Write 15: 0 to E2_DST_Y, Write 31: 16 to ", }, { col => undef, table => undef, text => "E2_DST_HEIGHT" }, { col => undef, table => undef, text => "[ W] (Reserved) 15: 0 DST_WIDTH 23: 16 Destination width: range 0 to 256 (ZERO extent)", }, ], }, { num => 6, text => [ { col => undef, table => undef, text => "Table 1-1 Register description table notation", }, { col => 0, table => 0, text => "Register Information" }, { col => 1, table => 0, text => "Example" }, { col => 0, table => 0, text => "Register name" }, { col => 1, table => 0, text => "DST_HEIGHT_WIDTH_8" }, { col => 0, table => 0, text => "Read / Write capability" }, { col => 0, table => 0, text => " R = Readable" }, { col => 0, table => 0, text => " W = Writable" }, { col => 0, table => 0, text => " RW = Readable and Writable" }, { col => 1, table => 0, text => "W" }, { col => 0, table => 0, text => "Register size" }, { col => 1, table => 0, text => "32 bits" }, { col => 0, table => 0, text => "Register address(es)*" }, { col => 1, table => 0, text => "MMReg:0x158C" }, { col => 0, table => 0, text => "Field name" }, { col => 1, table => 0, text => "DST_WIDTH" }, { col => 0, table => 0, text => "Field position/size" }, { col => 1, table => 0, text => "23:16" }, { col => 0, table => 0, text => "Field default value" }, { col => 1, table => 0, text => "0x0" }, { col => 0, table => 0, text => "Field description " }, { col => 1, table => 0, text => "Destination....complete" }, { col => 0, table => 0, text => "Field mirror information" }, { col => 1, table => 0, text => "(mirror bits 0:7 of DST_WIDTH:DST_WIDTH)", }, { col => 0, table => 0, text => "Brief register description" }, { col => 1, table => 0, text => "[ W] (Reserved) 15: 0 DST_WIDTH 23: 16 Destination width: range 0 to ", }, { col => 1, table => 0, text => "256 (ZERO extent)" }, { col => 0, table => 0, text => "* Note:" }, { col => 0, table => 0, text => "There may be more than one address; the convention used is as follows:", }, { col => 0, table => 0, text => " " }, { col => 0, table => 0, text => "[aperName:offset]" }, { col => 0, table => 0, text => " - single mapping, to one aperture/decode and one offset", }, { col => 0, table => 0, text => " " }, { col => 0, table => 0, text => "[aperName1, aperName2, \\205, aperNameN:offset]", }, { col => 0, table => 0, text => " - multiple mappings to different apertures/decodes but same offset", }, { col => 0, table => 0, text => " " }, { col => 0, table => 0, text => "[aperName:startOffset-endOffset]" }, { col => 0, table => 0, text => " - mapped to an offset range in the same aperture/decode", }, ], }, { num => 8, text => [ { col => undef, table => undef, text => "2.1" }, { col => undef, table => undef, text => "Memory Controller Registers" }, { col => "heading", table => 0, text => "MC_SEQ_CNTL - RW - 32 bits - [GpuF0MMReg:0x2600]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "MEM_ADDR_MAP_COLS" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=2**8 columns " }, { col => 3, table => 0, text => " 1=2**9 columns " }, { col => 3, table => 0, text => " 2=2**10 columns " }, { col => 3, table => 0, text => " 3=reserved " }, { col => 0, table => 0, text => "MEM_ADDR_MAP_BANK" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=4 banks " }, { col => 3, table => 0, text => " 1=8 banks " }, { col => 0, table => 0, text => "SAFE_MODE" }, { col => 1, table => 0, text => "5:4" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable safe mode " }, { col => 3, table => 0, text => " 1=Ensure closing all pages before doing refresh ", }, { col => 3, table => 0, text => " 2=Ensure closing page before access a different page in ", }, { col => 3, table => 0, text => "the same bank " }, { col => 3, table => 0, text => " 3=Reserved " }, { col => 0, table => 0, text => "CHANNEL_DISABLE" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " This field allows the user to " }, { col => 3, table => 0, text => "disable the mclk branch for the specific unused channel. ", }, { col => 3, table => 0, text => "NOT FOR 600 " }, { col => 0, table => 0, text => "PIPE_DELAY_OUT" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " " }, { col => 3, table => 0, text => "This field specifies pipeline " }, { col => 3, table => 0, text => "delay between mc & io. This field is NOT CONFIGURABLE ", }, { col => 3, table => 0, text => "for a specific ASIC " }, { col => 3, table => 0, text => "for 600: 0 " }, { col => 3, table => 0, text => "for " }, { col => 3, table => 0, text => "610: 0 " }, { col => 3, table => 0, text => "for 630: 1 " }, { col => 3, table => 0, text => " 0=No pipeline delay between MC/IO for outgoing signals ", }, { col => 3, table => 0, text => " 1=pipeline delay " }, { col => 0, table => 0, text => "PIPE_DELAY_IN" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " " }, { col => 3, table => 0, text => "This field specifies pipeline " }, { col => 3, table => 0, text => "delay between mc & io. This field is NOT CONFIGURABLE ", }, { col => 3, table => 0, text => "for a specific ASIC " }, { col => 3, table => 0, text => "for 600: 0 " }, { col => 3, table => 0, text => "for " }, { col => 3, table => 0, text => "610: 0 " }, { col => 3, table => 0, text => "for 630: 1 " }, { col => 3, table => 0, text => " 0=No pipeline delay between MC/IO for incoming signals ", }, { col => 3, table => 0, text => " 1=pipeline delay " }, { col => 0, table => 0, text => "MSKOFF_DAT_TL" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " " }, { col => 3, table => 0, text => "for the byte which has data " }, { col => 3, table => 0, text => "mask on, tie the corresponding dq to 0 ONLY 1 bit could be ", }, { col => 3, table => 0, text => "set to 1 among MSKOFF_DAT_TL, MSKOFF_DAT_TH, ", }, { col => 3, table => 0, text => "MSKOFF_DAT_AC " }, { col => 3, table => 0, text => " 1=Tie low for the DQ whose corresponding DQM is on ", }, { col => 0, table => 0, text => "MSKOFF_DAT_TH" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " " }, { col => 3, table => 0, text => "for the byte which has data " }, { col => 3, table => 0, text => "mask on, tie the corresponding dq to 1 ONLY 1 bit could be ", }, { col => 3, table => 0, text => "set to 1 among MSKOFF_DAT_TL, MSKOFF_DAT_TH, ", }, { col => 3, table => 0, text => "MSKOFF_DAT_AC " }, { col => 3, table => 0, text => " 1=Tie high for the DQ whose corresponding DQM is on ", }, { col => 0, table => 0, text => "MSKOFF_DAT_AC" }, { col => 1, table => 0, text => 18 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " " }, { col => 3, table => 0, text => "for the byte which has data " }, { col => 3, table => 0, text => "mask on, keep the previous dq value to avoid toggleing ", }, { col => 3, table => 0, text => "ONLY 1 bit could be set to 1 among MSKOFF_DAT_TL, ", }, { col => 3, table => 0, text => "MSKOFF_DAT_TH, MSKOFF_DAT_AC " }, { col => undef, table => undef, text => " 1=no toggling for the DQ whose corresponding DQM is on ", }, { col => undef, table => undef, text => " " }, { col => undef, table => undef, text => "This register specifies specific seq configuration ", }, { col => "heading", table => 1, text => "MC_SEQ_DRAM - RW - 32 bits - [GpuF0MMReg:0x2608]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "ADR_2CK" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Number of cycle(s) to send an address. One cycle ", }, { col => 3, table => 1, text => "for non-DDR4. Two cycles for DDR4.", }, { col => 3, table => 1, text => " 0=One-cycle address " }, { col => 3, table => 1, text => " 1=Two-cycle address " }, ], }, { num => 9, text => [ { col => 0, table => 0, text => "ADR_MUX" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Address bus is shared between two channels or not. ", }, { col => 3, table => 0, text => "Not shared for DDR4. Shared for non-DDR4.", }, { col => 3, table => 0, text => " 0=Address bus is not shared " }, { col => 3, table => 0, text => " 1=Address bus is shared " }, { col => 0, table => 0, text => "ADR_DF1" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Default value for address bus (during NOP).", }, { col => 3, table => 0, text => " 0=Address default low " }, { col => 3, table => 0, text => " 1=Address default high " }, { col => 0, table => 0, text => "AP8" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Location of auto-precharge bit.", }, { col => 3, table => 0, text => " 0=AP bit starts at MSB+1 " }, { col => 3, table => 0, text => " 1=AP bit is bit 8 " }, { col => 0, table => 0, text => "DAT_DF1" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Default value for data bus.", }, { col => 3, table => 0, text => " 0=DAT default low " }, { col => 3, table => 0, text => " 1=DAT default high " }, { col => 0, table => 0, text => "DQS_DF1" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Default value for write strobes.", }, { col => 3, table => 0, text => " 0=DQS default low " }, { col => 3, table => 0, text => " 1=DQS default high " }, { col => 0, table => 0, text => "DQM_DF1" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Default value for write mask.", }, { col => 3, table => 0, text => " 0=DQM default low " }, { col => 3, table => 0, text => " 1=DQM default high " }, { col => 0, table => 0, text => "DQM_ACT" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Polarity of data mask. Active low for DDR4. Active ", }, { col => 3, table => 0, text => "high for non- DDR4." }, { col => 3, table => 0, text => " 0=DQM active low " }, { col => 3, table => 0, text => " 1=DQM active high " }, { col => 0, table => 0, text => "STB_CNT" }, { col => 1, table => 0, text => "11:8" }, { col => 2, table => 0, text => "0xf" }, { col => 3, table => 0, text => " DRAM standby counter. Number of idle cycles ", }, { col => 3, table => 0, text => "before dynamic CKE is enabled. This prevents the ", }, { col => 3, table => 0, text => "CKE from turning off too easily." }, { col => 0, table => 0, text => "CKE_DYN" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Dynamic CKE." }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "CKE_ACT" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Polarity of clock enable. Active low for DDR4. Active ", }, { col => 3, table => 0, text => "high for non- DDR4." }, { col => 3, table => 0, text => " 0=Active low " }, { col => 3, table => 0, text => " 1=Active high " }, { col => 0, table => 0, text => "BO4" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " DRAM burst size." }, { col => 3, table => 0, text => " 0=DRAM is burst of 8 " }, { col => 3, table => 0, text => " 1=DRAM is burst of 4 " }, { col => 0, table => 0, text => "DLL_CLR" }, { col => 1, table => 0, text => 15 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Resets DLL lock timer. DRAM power up is ", }, { col => 3, table => 0, text => "completed once the DLL lock time is reached. If the ", }, { col => 3, table => 0, text => "DLL lock timer is reset, the DRAM power up flag is ", }, { col => 3, table => 0, text => "deasserted." }, { col => 3, table => 0, text => " 0=Not reset DLL timer " }, { col => 3, table => 0, text => " 1=Reset DLL timer " }, { col => 0, table => 0, text => "DLL_CNT" }, { col => 1, table => 0, text => "23:16" }, { col => 2, table => 0, text => "0xf" }, { col => 3, table => 0, text => " DRAM DLL lock time in multiples of 256 mclk cycles.", }, { col => 0, table => 0, text => "DAT_INV" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Enables/disables DDR write data inversion mode.", }, { col => 3, table => 0, text => " 0=Disable write data inversion " }, { col => 3, table => 0, text => " 1=Enable write data inversion " }, { col => 0, table => 0, text => "INV_ACM" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Selects DDR write data inversion mode.", }, { col => 3, table => 0, text => " 0=DC mode " }, { col => 3, table => 0, text => " 1=AC mode " }, { col => 0, table => 0, text => "ODT_ENB" }, { col => 1, table => 0, text => 26 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable ODT " }, { col => 3, table => 0, text => " 1=Enable ODT " }, { col => 0, table => 0, text => "ODT_ACT" }, { col => 1, table => 0, text => 27 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=ODT active low " }, { col => 3, table => 0, text => " 1=ODT active high " }, { col => 0, table => 0, text => "RST_CTL" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Controls DRAM reset pin. Channel B only.", }, { col => 3, table => 0, text => " 0=Drive reset low " }, { col => 3, table => 0, text => " 1=Drive reset high " }, { col => 0, table => 0, text => "TRI_MIO_DYN" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => " 1=Tristate cmd/data/addr during dynamic cke ", }, { col => undef, table => undef, text => " This register specifies the character of the DRAM interface.", }, ], }, { num => 10, text => [ { col => "heading", table => 0, text => "MC_SEQ_RAS_TIMING_P - RW - 32 bits - [GpuF0MMReg:0x260C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "TRCDW" }, { col => 1, table => 0, text => "4:0" }, { col => 2, table => 0, text => "0xa" }, { col => 3, table => 0, text => " Number of cycles from active to write - 1.", }, { col => 0, table => 0, text => "TRCDWA" }, { col => 1, table => 0, text => "9:5" }, { col => 2, table => 0, text => "0xa" }, { col => 3, table => 0, text => " Number of cycles from active to write with ", }, { col => 3, table => 0, text => "auto-precharge - 1. A special case for DDR1. ", }, { col => 3, table => 0, text => "Otherwise the same as TRCDW." }, { col => 0, table => 0, text => "TRCDR" }, { col => 1, table => 0, text => "14:10" }, { col => 2, table => 0, text => "0xd" }, { col => 3, table => 0, text => " Number of cycles from active to read - 1.", }, { col => 0, table => 0, text => "TRCDRA" }, { col => 1, table => 0, text => "19:15" }, { col => 2, table => 0, text => "0xd" }, { col => 3, table => 0, text => " Number of cycles from active to read with ", }, { col => 3, table => 0, text => "auto-precharge - 1. A special case for DDR1. ", }, { col => 3, table => 0, text => "Otherwise the same as TRCDR." }, { col => 0, table => 0, text => "TRRD" }, { col => 1, table => 0, text => "23:20" }, { col => 2, table => 0, text => "0x5" }, { col => 3, table => 0, text => " Number of cycles from active bank a to active bank ", }, { col => 3, table => 0, text => "b - 1." }, { col => 0, table => 0, text => "TRC" }, { col => 1, table => 0, text => "30:24" }, { col => 2, table => 0, text => "0x27" }, { col => 3, table => 0, text => " Number of cycles from active to active/auto refresh ", }, { col => undef, table => undef, text => "- 1." }, { col => undef, table => undef, text => " RAS related parameters in hclk cycles for performance mode.", }, { col => "heading", table => 1, text => "MC_SEQ_CAS_TIMING_P - RW - 32 bits - [GpuF0MMReg:0x2610]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TNOPW" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Extra cycle(s) between successive write bursts. For ", }, { col => 3, table => 1, text => "debugging purpose only." }, { col => 0, table => 1, text => "TNOPR" }, { col => 1, table => 1, text => "3:2" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Extra cycle(s) between successive read bursts. For ", }, { col => 3, table => 1, text => "debugging purpose only." }, { col => 0, table => 1, text => "TR2W" }, { col => 1, table => 1, text => "8:4" }, { col => 2, table => 1, text => "0x9" }, { col => 3, table => 1, text => " Read to write turn around time - 1.", }, { col => 0, table => 1, text => "TR2R" }, { col => 1, table => 1, text => "15:12" }, { col => 2, table => 1, text => "0x5" }, { col => 3, table => 1, text => " Read to read time - 1 (different rank).", }, { col => 0, table => 1, text => "TW2R" }, { col => 1, table => 1, text => "20:16" }, { col => 2, table => 1, text => "0x9" }, { col => 3, table => 1, text => " Write to read turn around time - 1.", }, { col => 0, table => 1, text => "TCL" }, { col => 1, table => 1, text => "28:24" }, { col => 2, table => 1, text => "0x6" }, { col => undef, table => undef, text => " CAS to data return latency - 2 (0 to 20).", }, { col => undef, table => undef, text => " CAS related paramters in hclk cycles for performance mode.", }, { col => "heading", table => 2, text => "MC_SEQ_MISC_TIMING_P - RW - 32 bits - [GpuF0MMReg:0x2614]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "TRP_WRA" }, { col => 1, table => 2, text => "5:0" }, { col => 2, table => 2, text => "0x15" }, { col => 3, table => 2, text => " From write with auto-prechrage to active - 1.", }, { col => 0, table => 2, text => "TCKE_HI" }, { col => 1, table => 2, text => "7:6" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " " }, { col => 3, table => 2, text => "2 MSB of " }, { col => 3, table => 2, text => "tCKE parameters, used to control exit power down time. ", }, { col => 0, table => 2, text => "TRP_RDA" }, { col => 1, table => 2, text => "13:8" }, { col => 2, table => 2, text => "0x11" }, { col => 3, table => 2, text => " From read with auto-prechrage to active - 1.", }, { col => 0, table => 2, text => "TRP" }, { col => 1, table => 2, text => "19:16" }, { col => 2, table => 2, text => "0xb" }, { col => 3, table => 2, text => " Precharge command period - 1.", }, { col => 0, table => 2, text => "TRFC" }, { col => 1, table => 2, text => "26:20" }, { col => 2, table => 2, text => "0x2f" }, { col => 3, table => 2, text => " Auto-refresh command period - 1.", }, { col => 0, table => 2, text => "TCKE" }, { col => 1, table => 2, text => "31:28" }, { col => 2, table => 2, text => "0x4" }, { col => undef, table => undef, text => " 4 LSB CKE power down exit timer.", }, { col => undef, table => undef, text => " Misc. DRAM parameters in hclk cycles for performance mode.", }, { col => "heading", table => 3, text => "MC_SEQ_MISC_TIMING2_P - RW - 32 bits - [GpuF0MMReg:0x2618]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "PA2RDATA" }, { col => 1, table => 3, text => "2:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " " }, { col => 3, table => 3, text => "Read " }, { col => 3, table => 3, text => "Preamble for DDR4. " }, { col => 0, table => 3, text => "PA2WDATA" }, { col => 1, table => 3, text => "6:4" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " Write " }, { col => 3, table => 3, text => "Preamble for DDR4. " }, { col => 0, table => 3, text => "FAW" }, { col => 1, table => 3, text => "12:8" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " Four Active " }, { col => 3, table => 3, text => "Window/2 - 5 in MCLK " }, ], }, { num => 11, text => [ { col => 0, table => 0, text => "TCKE_PULSE" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " minimum " }, { col => undef, table => undef, text => "power down period/power up period ", }, { col => undef, table => undef, text => " Misc. DRAM parameters in hclk cycles for performance mode.", }, { col => "heading", table => 1, text => "MC_SEQ_RAS_TIMING_B - RW - 32 bits - [GpuF0MMReg:0x261C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TRCDW" }, { col => 1, table => 1, text => "4:0" }, { col => 2, table => 1, text => "0xa" }, { col => 3, table => 1, text => " Number of cycles from active to write - 1.", }, { col => 0, table => 1, text => "TRCDWA" }, { col => 1, table => 1, text => "9:5" }, { col => 2, table => 1, text => "0xa" }, { col => 3, table => 1, text => " Number of cycles from active to write with ", }, { col => 3, table => 1, text => "auto-precharge - 1. A special case for DDR1. ", }, { col => 3, table => 1, text => "Otherwise the same as TRCDW." }, { col => 0, table => 1, text => "TRCDR" }, { col => 1, table => 1, text => "14:10" }, { col => 2, table => 1, text => "0xd" }, { col => 3, table => 1, text => " Number of cycles from active to read - 1.", }, { col => 0, table => 1, text => "TRCDRA" }, { col => 1, table => 1, text => "19:15" }, { col => 2, table => 1, text => "0xd" }, { col => 3, table => 1, text => " Number of cycles from active to read with ", }, { col => 3, table => 1, text => "auto-precharge - 1. A special case for DDR1. ", }, { col => 3, table => 1, text => "Otherwise the same as TRCDR." }, { col => 0, table => 1, text => "TRRD" }, { col => 1, table => 1, text => "23:20" }, { col => 2, table => 1, text => "0x5" }, { col => 3, table => 1, text => " Number of cycles from active bank a to active bank ", }, { col => 3, table => 1, text => "b - 1." }, { col => 0, table => 1, text => "TRC" }, { col => 1, table => 1, text => "30:24" }, { col => 2, table => 1, text => "0x27" }, { col => 3, table => 1, text => " Number of cycles from active to active/auto refresh ", }, { col => undef, table => undef, text => "- 1." }, { col => undef, table => undef, text => " RAS related parameters in hclk cycles for balanced mode", }, { col => "heading", table => 2, text => "MC_SEQ_CAS_TIMING_B - RW - 32 bits - [GpuF0MMReg:0x2620]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "TNOPW" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " Extra cycle(s) between successive write bursts. For ", }, { col => 3, table => 2, text => "debugging purpose only." }, { col => 0, table => 2, text => "TNOPR" }, { col => 1, table => 2, text => "3:2" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " Extra cycle(s) between successive read bursts. For ", }, { col => 3, table => 2, text => "debugging purpose only." }, { col => 0, table => 2, text => "TR2W" }, { col => 1, table => 2, text => "8:4" }, { col => 2, table => 2, text => "0x9" }, { col => 3, table => 2, text => " Read to write turn around time - 1.", }, { col => 0, table => 2, text => "TR2R" }, { col => 1, table => 2, text => "15:12" }, { col => 2, table => 2, text => "0x5" }, { col => 3, table => 2, text => " Read to read time - 1 (different rank).", }, { col => 0, table => 2, text => "TW2R" }, { col => 1, table => 2, text => "20:16" }, { col => 2, table => 2, text => "0x9" }, { col => 3, table => 2, text => " Write to read turn around time - 1.", }, { col => 0, table => 2, text => "TCL" }, { col => 1, table => 2, text => "28:24" }, { col => 2, table => 2, text => "0x6" }, { col => undef, table => undef, text => " CAS to data return latency - 2 (0 to 20).", }, { col => undef, table => undef, text => " CAS related paramters in hclk cycles for balanced mode.", }, { col => "heading", table => 3, text => "MC_SEQ_MISC_TIMING_B - RW - 32 bits - [GpuF0MMReg:0x2624]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "TRP_WRA" }, { col => 1, table => 3, text => "5:0" }, { col => 2, table => 3, text => "0x15" }, { col => 3, table => 3, text => " From write with auto-prechrage to active - 1.", }, { col => 0, table => 3, text => "TCKE_HI" }, { col => 1, table => 3, text => "7:6" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 2 MSB of " }, { col => 3, table => 3, text => "tCKE parameters, used to control exit power down time. ", }, { col => 0, table => 3, text => "TRP_RDA" }, { col => 1, table => 3, text => "13:8" }, { col => 2, table => 3, text => "0x11" }, { col => 3, table => 3, text => " From read with auto-prechrage to active - 1.", }, { col => 0, table => 3, text => "TRP" }, { col => 1, table => 3, text => "19:16" }, { col => 2, table => 3, text => "0xb" }, { col => 3, table => 3, text => " Precharge command period - 1.", }, { col => 0, table => 3, text => "TRFC" }, { col => 1, table => 3, text => "26:20" }, { col => 2, table => 3, text => "0x2f" }, { col => 3, table => 3, text => " Auto-refresh command period - 1.", }, { col => 0, table => 3, text => "TCKE" }, { col => 1, table => 3, text => "31:28" }, { col => 2, table => 3, text => "0x4" }, { col => undef, table => undef, text => " CKE power down exit timer.", }, { col => undef, table => undef, text => " Misc. DRAM parameters in hclk cycles for balanced mode.", }, { col => undef, table => undef, text => "MC_SEQ_MISC_TIMING2_B - RW - 32 bits - [GpuF0MMReg:0x2628]", }, ], }, { num => 12, text => [ { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "PA2RDATA" }, { col => 1, table => 0, text => "2:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Read " }, { col => 3, table => 0, text => "Preamble for DDR4. " }, { col => 0, table => 0, text => "PA2WDATA" }, { col => 1, table => 0, text => "6:4" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Write " }, { col => 3, table => 0, text => "Preamble for DDR4. " }, { col => 0, table => 0, text => "FAW" }, { col => 1, table => 0, text => "12:8" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "TCKE_PULSE" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " minimum " }, { col => undef, table => undef, text => "power down period/power up period ", }, { col => undef, table => undef, text => " Misc. DRAM parameters in hclk cycles for balanced mode.", }, { col => "heading", table => 1, text => "MC_SEQ_RAS_TIMING_S - RW - 32 bits - [GpuF0MMReg:0x262C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TRCDW" }, { col => 1, table => 1, text => "4:0" }, { col => 2, table => 1, text => "0xa" }, { col => 3, table => 1, text => " Number of cycles from active to write - 1.", }, { col => 0, table => 1, text => "TRCDWA" }, { col => 1, table => 1, text => "9:5" }, { col => 2, table => 1, text => "0xa" }, { col => 3, table => 1, text => " Number of cycles from active to write with ", }, { col => 3, table => 1, text => "auto-precharge - 1. A special case for DDR1. ", }, { col => 3, table => 1, text => "Otherwise the same as TRCDW." }, { col => 0, table => 1, text => "TRCDR" }, { col => 1, table => 1, text => "14:10" }, { col => 2, table => 1, text => "0xd" }, { col => 3, table => 1, text => " Number of cycles from active to read - 1.", }, { col => 0, table => 1, text => "TRCDRA" }, { col => 1, table => 1, text => "19:15" }, { col => 2, table => 1, text => "0xd" }, { col => 3, table => 1, text => " Number of cycles from active to read with ", }, { col => 3, table => 1, text => "auto-precharge - 1. A special case for DDR1. ", }, { col => 3, table => 1, text => "Otherwise the same as TRCDR." }, { col => 0, table => 1, text => "TRRD" }, { col => 1, table => 1, text => "23:20" }, { col => 2, table => 1, text => "0x5" }, { col => 3, table => 1, text => " Number of cycles from active bank a to active bank ", }, { col => 3, table => 1, text => "b - 1." }, { col => 0, table => 1, text => "TRC" }, { col => 1, table => 1, text => "30:24" }, { col => 2, table => 1, text => "0x27" }, { col => 3, table => 1, text => " Number of cycles from active to active/auto refresh ", }, { col => undef, table => undef, text => "- 1." }, { col => undef, table => undef, text => " RAS related parameters in hclk cycles for battery mode.", }, { col => "heading", table => 2, text => "MC_SEQ_CAS_TIMING_S - RW - 32 bits - [GpuF0MMReg:0x2630]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "TNOPW" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " Extra cycle(s) between successive write bursts. For ", }, { col => 3, table => 2, text => "debugging purpose only." }, { col => 0, table => 2, text => "TNOPR" }, { col => 1, table => 2, text => "3:2" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " Extra cycle(s) between successive read bursts. For ", }, { col => 3, table => 2, text => "debugging purpose only." }, { col => 0, table => 2, text => "TR2W" }, { col => 1, table => 2, text => "8:4" }, { col => 2, table => 2, text => "0x9" }, { col => 3, table => 2, text => " Read to write turn around time - 1.", }, { col => 0, table => 2, text => "TR2R" }, { col => 1, table => 2, text => "15:12" }, { col => 2, table => 2, text => "0x5" }, { col => 3, table => 2, text => " Read to read time - 1 (different rank).", }, { col => 0, table => 2, text => "TW2R" }, { col => 1, table => 2, text => "20:16" }, { col => 2, table => 2, text => "0x9" }, { col => 3, table => 2, text => " Write to read turn around time - 1.", }, { col => 0, table => 2, text => "TCL" }, { col => 1, table => 2, text => "28:24" }, { col => 2, table => 2, text => "0x6" }, { col => undef, table => undef, text => " CAS to data return latency - 2 (0 to 20).", }, { col => undef, table => undef, text => " CAS related paramters in hclk cycles for battery mode.", }, { col => "heading", table => 3, text => "MC_SEQ_MISC_TIMING_S - RW - 32 bits - [GpuF0MMReg:0x2634]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "TRP_WRA" }, { col => 1, table => 3, text => "5:0" }, { col => 2, table => 3, text => "0x15" }, { col => 3, table => 3, text => " From write with auto-prechrage to active - 1.", }, { col => 0, table => 3, text => "TCKE_HI" }, { col => 1, table => 3, text => "7:6" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " " }, { col => 3, table => 3, text => "2 MSB of " }, { col => 3, table => 3, text => "tCKE parameters, used to control exit power down time. ", }, { col => 0, table => 3, text => "TRP_RDA" }, { col => 1, table => 3, text => "13:8" }, { col => 2, table => 3, text => "0x11" }, { col => 3, table => 3, text => " From read with auto-prechrage to active - 1.", }, { col => 0, table => 3, text => "TRP" }, { col => 1, table => 3, text => "19:16" }, { col => 2, table => 3, text => "0xb" }, { col => 3, table => 3, text => " Precharge command period - 1.", }, { col => 0, table => 3, text => "TRFC" }, { col => 1, table => 3, text => "26:20" }, { col => 2, table => 3, text => "0x2f" }, { col => 3, table => 3, text => " Auto-refresh command period - 1.", }, { col => 0, table => 3, text => "TCKE" }, { col => 1, table => 3, text => "31:28" }, { col => 2, table => 3, text => "0x4" }, { col => undef, table => undef, text => " CKE power down exit timer.", }, { col => undef, table => undef, text => " Misc. DRAM parameters in hclk cycles for battery mode.", }, ], }, { num => 13, text => [ { col => "heading", table => 0, text => "MC_SEQ_MISC_TIMING2_S - RW - 32 bits - [GpuF0MMReg:0x2638]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "PA2RDATA" }, { col => 1, table => 0, text => "2:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Read " }, { col => 3, table => 0, text => "Preamble for DDR4. " }, { col => 0, table => 0, text => "PA2WDATA" }, { col => 1, table => 0, text => "6:4" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Write " }, { col => 3, table => 0, text => "Preamble for DDR4. " }, { col => 0, table => 0, text => "FAW" }, { col => 1, table => 0, text => "12:8" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "TCKE_PULSE" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " minimum " }, { col => undef, table => undef, text => "power down period/power up period ", }, { col => undef, table => undef, text => " Misc. DRAM parameters in hclk cycles for battery mode.", }, { col => "heading", table => 1, text => "MC_SEQ_RAS_TIMING_C - RW - 32 bits - [GpuF0MMReg:0x263C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TRCDW" }, { col => 1, table => 1, text => "4:0" }, { col => 2, table => 1, text => "0xa" }, { col => 3, table => 1, text => " Number of cycles from active to write - 1.", }, { col => 0, table => 1, text => "TRCDWA" }, { col => 1, table => 1, text => "9:5" }, { col => 2, table => 1, text => "0xa" }, { col => 3, table => 1, text => " Number of cycles from active to write with ", }, { col => 3, table => 1, text => "auto-precharge - 1. A special case for DDR1. ", }, { col => 3, table => 1, text => "Otherwise the same as TRCDW." }, { col => 0, table => 1, text => "TRCDR" }, { col => 1, table => 1, text => "14:10" }, { col => 2, table => 1, text => "0xd" }, { col => 3, table => 1, text => " Number of cycles from active to read - 1.", }, { col => 0, table => 1, text => "TRCDRA" }, { col => 1, table => 1, text => "19:15" }, { col => 2, table => 1, text => "0xd" }, { col => 3, table => 1, text => " Number of cycles from active to read with ", }, { col => 3, table => 1, text => "auto-precharge - 1. A special case for DDR1. ", }, { col => 3, table => 1, text => "Otherwise the same as TRCDR." }, { col => 0, table => 1, text => "TRRD" }, { col => 1, table => 1, text => "23:20" }, { col => 2, table => 1, text => "0x5" }, { col => 3, table => 1, text => " Number of cycles from active bank a to active bank ", }, { col => 3, table => 1, text => "b - 1." }, { col => 0, table => 1, text => "TRC" }, { col => 1, table => 1, text => "30:24" }, { col => 2, table => 1, text => "0x27" }, { col => 3, table => 1, text => " Number of cycles from active to active/auto refresh ", }, { col => undef, table => undef, text => "- 1." }, { col => undef, table => undef, text => " RAS related parameters in hclk cycles for context switch mode for context switch mode.", }, { col => "heading", table => 2, text => "MC_SEQ_CAS_TIMING_C - RW - 32 bits - [GpuF0MMReg:0x2640]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "TNOPW" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " Extra cycle(s) between successive write bursts. For ", }, { col => 3, table => 2, text => "debugging purpose only." }, { col => 0, table => 2, text => "TNOPR" }, { col => 1, table => 2, text => "3:2" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " Extra cycle(s) between successive read bursts. For ", }, { col => 3, table => 2, text => "debugging purpose only." }, { col => 0, table => 2, text => "TR2W" }, { col => 1, table => 2, text => "8:4" }, { col => 2, table => 2, text => "0x9" }, { col => 3, table => 2, text => " Read to write turn around time - 1.", }, { col => 0, table => 2, text => "TR2R" }, { col => 1, table => 2, text => "15:12" }, { col => 2, table => 2, text => "0x5" }, { col => 3, table => 2, text => " Read to read time - 1 (different rank).", }, { col => 0, table => 2, text => "TW2R" }, { col => 1, table => 2, text => "20:16" }, { col => 2, table => 2, text => "0x9" }, { col => 3, table => 2, text => " Write to read turn around time - 1.", }, { col => 0, table => 2, text => "TCL" }, { col => 1, table => 2, text => "28:24" }, { col => 2, table => 2, text => "0x6" }, { col => undef, table => undef, text => " CAS to data return latency - 2 (0 to 20).", }, { col => undef, table => undef, text => " CAS related paramters in hclk cycles for context switch mode.", }, { col => "heading", table => 3, text => "MC_SEQ_MISC_TIMING_C - RW - 32 bits - [GpuF0MMReg:0x2644]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "TRP_WRA" }, { col => 1, table => 3, text => "5:0" }, { col => 2, table => 3, text => "0x15" }, { col => 3, table => 3, text => " From write with auto-prechrage to active - 1.", }, { col => 0, table => 3, text => "TCKE_HI" }, { col => 1, table => 3, text => "7:6" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 2 MSB of " }, { col => 3, table => 3, text => "tCKE parameters, used to control exit power down time. ", }, { col => 0, table => 3, text => "TRP_RDA" }, { col => 1, table => 3, text => "13:8" }, { col => 2, table => 3, text => "0x11" }, { col => 3, table => 3, text => " From read with auto-prechrage to active - 1.", }, ], }, { num => 14, text => [ { col => 0, table => 0, text => "TRP" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0xb" }, { col => 3, table => 0, text => " Precharge command period - 1.", }, { col => 0, table => 0, text => "TRFC" }, { col => 1, table => 0, text => "26:20" }, { col => 2, table => 0, text => "0x2f" }, { col => 3, table => 0, text => " Auto-refresh command period - 1.", }, { col => 0, table => 0, text => "TCKE" }, { col => 1, table => 0, text => "31:28" }, { col => 2, table => 0, text => "0x4" }, { col => undef, table => undef, text => " CKE power down exit timer.", }, { col => undef, table => undef, text => " Misc. DRAM parameters in hclk cycles for context switch mode.", }, { col => "heading", table => 1, text => "MC_SEQ_MISC_TIMING2_C - RW - 32 bits - [GpuF0MMReg:0x2648]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "PA2RDATA" }, { col => 1, table => 1, text => "2:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Read " }, { col => 3, table => 1, text => "Preamble for DDR4. " }, { col => 0, table => 1, text => "PA2WDATA" }, { col => 1, table => 1, text => "6:4" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Write " }, { col => 3, table => 1, text => "Preamble for DDR4. " }, { col => 0, table => 1, text => "FAW" }, { col => 1, table => 1, text => "12:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "TCKE_PULSE" }, { col => 1, table => 1, text => "19:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " minimum " }, { col => undef, table => undef, text => "power down period/power up period ", }, { col => undef, table => undef, text => " Misc. DRAM parameters in hclk cycles for context switch mode.", }, { col => "heading", table => 2, text => "MC_SEQ_CMD - RW - 32 bits - [GpuF0MMReg:0x26C4]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "ADR" }, { col => 1, table => 2, text => "15:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " This field is mapped directly to the address bus.", }, { col => 0, table => 2, text => "MOP" }, { col => 1, table => 2, text => "18:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " DRAM command." }, { col => 3, table => 2, text => " 0=NOP " }, { col => 3, table => 2, text => " 1=Load mode register " }, { col => 3, table => 2, text => " 2=Precharge " }, { col => 3, table => 2, text => " 3=Auto-refresh " }, { col => 3, table => 2, text => " 4=Self-refresh " }, { col => 0, table => 2, text => "END" }, { col => 1, table => 2, text => 20 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " If set, the DLL lock timer starts counting. Once it ", }, { col => 3, table => 2, text => "reaches a pre- defined value, the DLL is stabilized ", }, { col => 3, table => 2, text => "and DRAM power up sequence is completed. See ", }, { col => 3, table => 2, text => "also DLL_CNT inside MC_SEQ_DRAM." }, { col => 3, table => 2, text => " 0=Not last operation " }, { col => 3, table => 2, text => " 1=Last operation, wait for DLL to stabilize ", }, { col => 0, table => 2, text => "CSB" }, { col => 1, table => 2, text => "22:21" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " Allows rank 0 and rank 1 to be selected ", }, { col => 3, table => 2, text => "independently." }, { col => 3, table => 2, text => " 0=Select both ranks " }, { col => 3, table => 2, text => " 1=Select rank 1 " }, { col => 3, table => 2, text => " 2=Select rank 0 " }, { col => 3, table => 2, text => " 3=Select none " }, { col => 0, table => 2, text => "CHAN0" }, { col => 1, table => 2, text => 24 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Select channel 0 " }, { col => 3, table => 2, text => " 1=Not select channel 0 " }, { col => 0, table => 2, text => "CHAN1" }, { col => 1, table => 2, text => 25 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Select channel 1 " }, { col => undef, table => undef, text => " 1=Not select channel 1 " }, { col => undef, table => undef, text => " Command register for DRAM initialization.", }, { col => "heading", table => 3, text => "MC_PMG_CMD - RW - 32 bits - [GpuF0MMReg:0x26CC]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "ADR" }, { col => 1, table => 3, text => "15:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " The value of the mode register for resetting DRAM ", }, { col => 3, table => 3, text => "DLL." }, ], }, { num => 15, text => [ { col => 0, table => 0, text => "MOP" }, { col => 1, table => 0, text => "18:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Operation" }, { col => 3, table => 0, text => " 0=NOP " }, { col => 3, table => 0, text => " 1=Reset DLL " }, { col => 3, table => 0, text => " 2=Precharge All " }, { col => 3, table => 0, text => " 3=Auto-refresh " }, { col => 3, table => 0, text => " 4=Self-refresh " }, { col => 0, table => 0, text => "END" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " This field is not used." }, { col => 3, table => 0, text => " 0=Not last operation " }, { col => 3, table => 0, text => " 1=Last operation, wait for DLL to stabilize ", }, { col => 0, table => 0, text => "CSB" }, { col => 1, table => 0, text => "22:21" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " This field is not used." }, { col => 3, table => 0, text => " 0=Select both ranks " }, { col => 3, table => 0, text => " 1=Select rank 1 " }, { col => 3, table => 0, text => " 2=Select rank 0 " }, { col => undef, table => undef, text => " 3=Select none " }, { col => undef, table => undef, text => " Power manager command register. This register specifies the value used for resetting the DRAM DLL.", }, { col => "heading", table => 1, text => "MC_PMG_CFG - RW - 32 bits - [GpuF0MMReg:0x26D0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "SYC_CLK" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Controls mclk/yclk synchronization after on-chip ", }, { col => 3, table => 1, text => "DLL is reset." }, { col => 3, table => 1, text => " 0=Don't synchronize YCLK/MCLK after DLL is reset ", }, { col => 3, table => 1, text => " 1=Synchronize YCLK/MCLK after DLL is reset ", }, { col => 0, table => 1, text => "RST_DLL" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Controls DRAM DLL reset after waking up from ", }, { col => 3, table => 1, text => "self-refresh." }, { col => 3, table => 1, text => " 0=Don't reset DRAM DLL after self-refresh ", }, { col => 3, table => 1, text => " 1=Reset DRAM DLL after self-refresh " }, { col => 0, table => 1, text => "TRI_MIO" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Controls memory IO tristate during power down.", }, { col => 3, table => 1, text => " 0=Don't tri-state DRAM CMD and CLK signals dring ", }, { col => 3, table => 1, text => "self-refresh " }, { col => 3, table => 1, text => " 1=tri-state DRAM CMD and CLK signals druing ", }, { col => 3, table => 1, text => "self-refresh " }, { col => 0, table => 1, text => "XSR_TMR" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Multiple of 16 mclk cycles to wait before resetting ", }, { col => 3, table => 1, text => "DRAM DLL." }, { col => 0, table => 1, text => "AUTO_SLF" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Enable " }, { col => 3, table => 1, text => "automatic selfrefresh mode " }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "AUTO_SLF_IDLE_CNT" }, { col => 1, table => 1, text => "15:12" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Number of " }, { col => 3, table => 1, text => "idle cycles memory stays before put the memory into self ", }, { col => 3, table => 1, text => "refresh mode " }, { col => 3, table => 1, text => " 1=256*2 " }, { col => 3, table => 1, text => " 2=256*3 " }, { col => 3, table => 1, text => " 3=256*4 " }, { col => 3, table => 1, text => " 4=256*5 " }, { col => 3, table => 1, text => " 5=256*6 " }, { col => 3, table => 1, text => " 6=256*7 " }, { col => 3, table => 1, text => " 7=256*8 " }, { col => 3, table => 1, text => " 8=256*9 " }, { col => 3, table => 1, text => " 9=256*10 " }, { col => 3, table => 1, text => " 10=256*11 " }, { col => 3, table => 1, text => " 11=256*12 " }, { col => 3, table => 1, text => " 12=256*13 " }, { col => 3, table => 1, text => " 13=256*14 " }, { col => 3, table => 1, text => " 14=256*15 " }, { col => 0, table => 1, text => "SLF_IDLE_CNT" }, { col => 1, table => 1, text => "19:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Number of " }, { col => 3, table => 1, text => "SEQ idle cycles after SEQ receiving self-refresh command ", }, { col => 3, table => 1, text => "to the time SEQ issue the self-refresh command - 16 ", }, ], }, { num => 16, text => [ { col => 0, table => 0, text => "WRITE_DURING_DLOCK" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=no write during dll lock time " }, { col => 3, table => 0, text => " 1=allow write transaction during dll lock time ", }, { col => 0, table => 0, text => "EARLY_ACK_DYN" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=ack out-of-slf when DLL is locked " }, { col => 3, table => 0, text => " 1=ack out-of-slf when tXSNR expires " }, { col => 0, table => 0, text => "EARLY_ACK_ACPI" }, { col => 1, table => 0, text => 22 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=ack out-of-slf when DLL is locked " }, { col => 3, table => 0, text => " 1=ack out-of-slf when tXSNR expires " }, { col => 0, table => 0, text => "UNUSED_SEQ_SHUTDOWN" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=keep mclk branch running for unused SEQ pair ", }, { col => undef, table => undef, text => " 1=shut off unused SEQ pair " }, { col => undef, table => undef, text => " Power manager configuration register.", }, { col => "heading", table => 1, text => "MC_IMP_CNTL - RW - 32 bits - [GpuF0MMReg:0x26D4]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "MEM_IO_UPDATE_RATE" }, { col => 1, table => 1, text => "4:0" }, { col => 2, table => 1, text => "0x16" }, { col => 3, table => 1, text => "Update the impedance value to the PMTEST every ", }, { col => 3, table => 1, text => "2^MEM_IO_UPDATE_DELAY cycles" }, { col => 0, table => 1, text => "MEM_IO_PMCOMP_STRD2" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "MEM_IO_SAMPLE_DELAY" }, { col => 1, table => 1, text => "12:8" }, { col => 2, table => 1, text => "0x6" }, { col => 3, table => 1, text => "Calibration Unit will sample every " }, { col => 3, table => 1, text => "2^MEM_IO_SAMPLE_DELAY cycles" }, { col => 0, table => 1, text => "MEM_IO_SAMPLE_CNT" }, { col => 1, table => 1, text => "15:13" }, { col => 2, table => 1, text => "0x7" }, { col => 3, table => 1, text => "Number of samples to be taken before update value to IO", }, { col => 0, table => 1, text => "MEM_IO_INC_THRESHOLD" }, { col => 1, table => 1, text => "20:16" }, { col => 2, table => 1, text => "0xe" }, { col => 3, table => 1, text => "Number of '1' get detected during 15 cycles before increase ", }, { col => 3, table => 1, text => "impedance value" }, { col => 0, table => 1, text => "MEM_IO_DEC_THRESHOLD" }, { col => 1, table => 1, text => "28:24" }, { col => 2, table => 1, text => "0x6" }, { col => 3, table => 1, text => "Number of '0' get detected during 15 cycles before ", }, { col => 3, table => 1, text => "decrease impedance value" }, { col => 0, table => 1, text => "CAL_WHEN_IDLE" }, { col => 1, table => 1, text => 29 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "CAL_WHEN_REFRESH" }, { col => 1, table => 1, text => 30 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "MEM_IMP_EN" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "Impedance Calibration Control" }, { col => "heading", table => 2, text => "MC_IMP_DEBUG - RW - 32 bits - [GpuF0MMReg:0x2878]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "MEM_IMP_DEBUG_N" }, { col => 1, table => 2, text => "3:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "MEM_IMP_DEBUG_P" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "MEM_IO_IMP_DEBUG_EN" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "MEM_STATUS_SEL" }, { col => 1, table => 2, text => 12 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Vertical " }, { col => 3, table => 2, text => " 1=Horizontal " }, { col => "heading", table => 3, text => "MC_IMP_STATUS - RW - 32 bits - [GpuF0MMReg:0x2874]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "IMP_N_MEM_DQ_SN_I0 (R)" }, { col => 1, table => 3, text => "3:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "IMP_P_MEM_DQ_SP_I0 (R)" }, { col => 1, table => 3, text => "7:4" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "IMP_N_MEM_DQ_SN_I1 (R)" }, { col => 1, table => 3, text => "11:8" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "IMP_P_MEM_DQ_SP_I1 (R)" }, { col => 1, table => 3, text => "15:12" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "IMP_N_VALUE_R_BACK (R)" }, { col => 1, table => 3, text => "19:16" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "IMP_P_VALUE_R_BACK (R)" }, { col => 1, table => 3, text => "23:20" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "IMP_CAL_COUNT (R)" }, { col => 1, table => 3, text => "27:24" }, { col => 2, table => 3, text => "0x0" }, ], }, { num => 17, text => [ { col => 0, table => 0, text => "TEST_OUT_R_BACK (R)" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DUMMY_OUT_R_BACK (R)" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_PAD_CNTL - RW - 32 bits - [GpuF0MMReg:0x2700]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VREFI_VCO_EN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "IMP_VREF_INTR" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "IMP_VREF_INTN" }, { col => 1, table => 1, text => "3:2" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "IMP_VREF_INTP" }, { col => 1, table => 1, text => "5:4" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "MC_SEQ_RD_CTL_D0_P - RW - 32 bits - [GpuF0MMReg:0x264C]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "RCV_DLY" }, { col => undef, table => undef, text => "2:0" }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " Delay to turn on receive enable.", }, { col => undef, table => undef, text => " 0=Turn on receive enable at CL-2 ", }, { col => undef, table => undef, text => " 1=Turn on receive enable at CL-1 ", }, { col => undef, table => undef, text => " 2=Turn on receive enable at CL ", }, { col => undef, table => undef, text => " 3=Turn on receive enable at CL+1 ", }, { col => undef, table => undef, text => " 4=Turn on receive enable at CL+2 ", }, { col => undef, table => undef, text => " 5=Turn on receive enable at CL+3 ", }, { col => undef, table => undef, text => " 6=Turn on receive enable at CL+4 ", }, { col => undef, table => undef, text => " 7=Turn on receive enable at CL+5 ", }, { col => undef, table => undef, text => "RCV_EXT" }, { col => undef, table => undef, text => "7:4" }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " Extends receive enable signal to cover clock drift.", }, { col => undef, table => undef, text => " 0=DQS receive enable not extended ", }, { col => undef, table => undef, text => " 1=DQS receive enable extended by 1 cycle ", }, { col => undef, table => undef, text => " 2=DQS receive enable extended by 2 cycles ", }, { col => undef, table => undef, text => " 3=DQS receive enable extended by 3 cycles ", }, { col => undef, table => undef, text => " 4=DQS receive enable extended by 4 cycles ", }, { col => undef, table => undef, text => " 5=DQS receive enable extended by 5 cycles ", }, { col => undef, table => undef, text => " 6=DQS receive enable extended by 6 cycles ", }, { col => undef, table => undef, text => " 7=DQS receive enable extended by 7 cycles ", }, { col => undef, table => undef, text => " 8=DQS receive enable always on ", }, { col => undef, table => undef, text => "RST_SEL" }, { col => undef, table => undef, text => "9:8" }, { col => undef, table => undef, text => "0x2" }, { col => undef, table => undef, text => " NPL FIFO pointer reset mode.", }, { col => undef, table => undef, text => " 0=Reset pointers off " }, { col => undef, table => undef, text => " 1=Reset pointers on " }, { col => undef, table => undef, text => " 2=Reset pointers before read ", }, { col => undef, table => undef, text => " 3=Reset pointers during refresh ", }, ], }, { num => 18, text => [ { col => 0, table => 0, text => "RST_HLD" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Disables NPL FIFO pointer reset after a read ", }, { col => 3, table => 0, text => "command for a certain period of time. This prevents ", }, { col => 3, table => 0, text => "the pointers (read and write) from resetting before ", }, { col => 3, table => 0, text => "the FIFO is read." }, { col => 3, table => 0, text => " 0=Disable reset by 11 cycles " }, { col => 3, table => 0, text => " 1=Disable reset by 12 cycles " }, { col => 3, table => 0, text => " 2=Disable reset by 13 cycles " }, { col => 3, table => 0, text => " 3=Disable reset by 14 cycles " }, { col => 3, table => 0, text => " 4=Disable reset by 15 cycles " }, { col => 3, table => 0, text => " 5=Disable reset by 16 cycles " }, { col => 3, table => 0, text => " 6=Disable reset by 17 cycles " }, { col => 3, table => 0, text => " 7=Disable reset by 18 cycles " }, { col => 3, table => 0, text => " 8=Disable reset by 19 cycles " }, { col => 3, table => 0, text => " 9=Disable reset by 20 cycles " }, { col => 3, table => 0, text => " 10=Disable reset by 21 cycles " }, { col => 3, table => 0, text => " 11=Disable reset by 22 cycles " }, { col => 3, table => 0, text => " 12=Disable reset by 23 cycles " }, { col => 3, table => 0, text => " 13=Disable reset by 24 cycles " }, { col => 3, table => 0, text => " 14=Disable reset by 25 cycles " }, { col => 0, table => 0, text => "STR_PRE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Creates an extra strobe in the preamble of a burst. ", }, { col => 3, table => 0, text => "This is needed if DQS is default high and its falling ", }, { col => 3, table => 0, text => "edge is used as a trigger." }, { col => 3, table => 0, text => " 0=No read pre strobe " }, { col => 3, table => 0, text => " 1=Extra read pre strobe " }, { col => 0, table => 0, text => "STR_PST" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Creates an extra strobe in the postamble of a burst. ", }, { col => 3, table => 0, text => "This is needed if DQS is default high and its rising ", }, { col => 3, table => 0, text => "edge is used as a trigger." }, { col => 3, table => 0, text => " 0=No read post strobe " }, { col => 3, table => 0, text => " 1=Extra read post strobe " }, { col => 0, table => 0, text => "RBS_DLY" }, { col => 1, table => 0, text => "24:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Delay to read data out of a NPL FIFO. This is used ", }, { col => 3, table => 0, text => "to cover the NPL FIFO's write to read latency.", }, { col => 3, table => 0, text => " 0=Assert RBS valid at CL+8 " }, { col => 3, table => 0, text => " 1=Assert RBS valid at CL+9 " }, { col => 3, table => 0, text => " 2=Assert RBS valid at CL+10 " }, { col => 3, table => 0, text => " 3=Assert RBS valid at CL+11 " }, { col => 3, table => 0, text => " 4=Assert RBS valid at CL+12 " }, { col => 3, table => 0, text => " 5=Assert RBS valid at CL+13 " }, { col => 3, table => 0, text => " 6=Assert RBS valid at CL+14 " }, { col => 3, table => 0, text => " 7=Assert RBS valid at CL+15 " }, { col => 3, table => 0, text => " 8=Assert RBS valid at CL+16 " }, { col => 3, table => 0, text => " 9=Assert RBS valid at CL+17 " }, { col => 3, table => 0, text => " 10=Assert RBS valid at CL+18 " }, { col => 3, table => 0, text => " 11=Assert RBS valid at CL+19 " }, { col => 3, table => 0, text => " 12=Assert RBS valid at CL+20 " }, { col => 3, table => 0, text => " 13=Assert RBS valid at CL+21 " }, { col => 3, table => 0, text => " 14=Assert RBS valid at CL+22 " }, { col => 3, table => 0, text => " 15=Assert RBS valid at CL+23 " }, { col => 3, table => 0, text => " 16=Assert RBS valid at CL+24 " }, { col => undef, table => undef, text => " 17=Assert RBS valid at CL+25 " }, { col => undef, table => undef, text => " Channel 0's read command parameters in hclk.", }, { col => "heading", table => 1, text => "MC_SEQ_RD_CTL_D1_P - RW - 32 bits - [GpuF0MMReg:0x2650]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, ], }, { num => 19, text => [ { col => 0, table => 0, text => "RCV_DLY" }, { col => 1, table => 0, text => "2:0" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=Turn on receive enable at CL-2 " }, { col => 3, table => 0, text => " 1=Turn on receive enable at CL-1 " }, { col => 3, table => 0, text => " 2=Turn on receive enable at CL " }, { col => 3, table => 0, text => " 3=Turn on receive enable at CL+1 " }, { col => 3, table => 0, text => " 4=Turn on receive enable at CL+2 " }, { col => 3, table => 0, text => " 5=Turn on receive enable at CL+3 " }, { col => 3, table => 0, text => " 6=Turn on receive enable at CL+4 " }, { col => 3, table => 0, text => " 7=Turn on receive enable at CL+5 " }, { col => 0, table => 0, text => "RCV_EXT" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=DQS receive enable not extended " }, { col => 3, table => 0, text => " 1=DQS receive enable extended by 1 cycle ", }, { col => 3, table => 0, text => " 2=DQS receive enable extended by 2 cycles ", }, { col => 3, table => 0, text => " 3=DQS receive enable extended by 3 cycles ", }, { col => 3, table => 0, text => " 4=DQS receive enable extended by 4 cycles ", }, { col => 3, table => 0, text => " 5=DQS receive enable extended by 5 cycles ", }, { col => 3, table => 0, text => " 6=DQS receive enable extended by 6 cycles ", }, { col => 3, table => 0, text => " 7=DQS receive enable extended by 7 cycles ", }, { col => 3, table => 0, text => " 8=DQS receive enable always on " }, { col => 0, table => 0, text => "RST_SEL" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => " 0=Reset pointers off " }, { col => 3, table => 0, text => " 1=Reset pointers on " }, { col => 3, table => 0, text => " 2=Reset pointers before read " }, { col => 3, table => 0, text => " 3=Reset pointers during refresh " }, { col => 0, table => 0, text => "RST_HLD" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable reset by 11 cycles " }, { col => 3, table => 0, text => " 1=Disable reset by 12 cycles " }, { col => 3, table => 0, text => " 2=Disable reset by 13 cycles " }, { col => 3, table => 0, text => " 3=Disable reset by 14 cycles " }, { col => 3, table => 0, text => " 4=Disable reset by 15 cycles " }, { col => 3, table => 0, text => " 5=Disable reset by 16 cycles " }, { col => 3, table => 0, text => " 6=Disable reset by 17 cycles " }, { col => 3, table => 0, text => " 7=Disable reset by 18 cycles " }, { col => 3, table => 0, text => " 8=Disable reset by 19 cycles " }, { col => 3, table => 0, text => " 9=Disable reset by 20 cycles " }, { col => 3, table => 0, text => " 10=Disable reset by 21 cycles " }, { col => 3, table => 0, text => " 11=Disable reset by 22 cycles " }, { col => 3, table => 0, text => " 12=Disable reset by 23 cycles " }, { col => 3, table => 0, text => " 13=Disable reset by 24 cycles " }, { col => 3, table => 0, text => " 14=Disable reset by 25 cycles " }, { col => 0, table => 0, text => "STR_PRE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read pre strobe " }, { col => 3, table => 0, text => " 1=Extra read pre strobe " }, { col => 0, table => 0, text => "STR_PST" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read post strobe " }, { col => 3, table => 0, text => " 1=Extra read post strobe " }, { col => 0, table => 0, text => "RBS_DLY" }, { col => 1, table => 0, text => "24:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Assert RBS valid at CL+8 " }, { col => 3, table => 0, text => " 1=Assert RBS valid at CL+9 " }, { col => 3, table => 0, text => " 2=Assert RBS valid at CL+10 " }, { col => 3, table => 0, text => " 3=Assert RBS valid at CL+11 " }, { col => 3, table => 0, text => " 4=Assert RBS valid at CL+12 " }, { col => 3, table => 0, text => " 5=Assert RBS valid at CL+13 " }, { col => 3, table => 0, text => " 6=Assert RBS valid at CL+14 " }, { col => 3, table => 0, text => " 7=Assert RBS valid at CL+15 " }, { col => 3, table => 0, text => " 8=Assert RBS valid at CL+16 " }, { col => 3, table => 0, text => " 9=Assert RBS valid at CL+17 " }, { col => 3, table => 0, text => " 10=Assert RBS valid at CL+18 " }, { col => 3, table => 0, text => " 11=Assert RBS valid at CL+19 " }, { col => 3, table => 0, text => " 12=Assert RBS valid at CL+20 " }, { col => 3, table => 0, text => " 13=Assert RBS valid at CL+21 " }, { col => 3, table => 0, text => " 14=Assert RBS valid at CL+22 " }, { col => 3, table => 0, text => " 15=Assert RBS valid at CL+23 " }, { col => 3, table => 0, text => " 16=Assert RBS valid at CL+24 " }, { col => undef, table => undef, text => " 17=Assert RBS valid at CL+25 " }, { col => undef, table => undef, text => " Channel 1's read command parameters in hclk. See MC_SEQ_RD_CTL_I0.", }, ], }, { num => 20, text => [ { col => "heading", table => 0, text => "MC_SEQ_WR_CTL_D0_P - RW - 32 bits - [GpuF0MMReg:0x2654]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DAT_DLY" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x3" }, { col => 3, table => 0, text => " Write command to data output latency.", }, { col => 0, table => 0, text => "DQS_DLY" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x3" }, { col => 3, table => 0, text => " Write command to DQS latency.", }, { col => 0, table => 0, text => "DQS_XTR" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Controls write preamble." }, { col => 3, table => 0, text => " 0=No write preamble " }, { col => 3, table => 0, text => " 1=Write preamble " }, { col => 0, table => 0, text => "OEN_DLY" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x3" }, { col => 3, table => 0, text => " Write command to output enable latency.", }, { col => 0, table => 0, text => "OEN_EXT" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Extends output enable after data burst.", }, { col => 3, table => 0, text => " 0=output enable not extended " }, { col => 3, table => 0, text => " 1=output eanble extended by one cycle ", }, { col => 0, table => 0, text => "OEN_SEL" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "ODT_DLY" }, { col => 1, table => 0, text => "27:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Write command to on-die-termination enable ", }, { col => 3, table => 0, text => "latency." }, { col => 0, table => 0, text => "ODT_EXT" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Extends on-die-termination enable after data burst.", }, { col => 3, table => 0, text => " 0=ODT not extended " }, { col => undef, table => undef, text => " 1=ODT extended by one cycle " }, { col => undef, table => undef, text => " Channel 0's write command parameters in hclk.", }, { col => "heading", table => 1, text => "MC_SEQ_WR_CTL_D1_P - RW - 32 bits - [GpuF0MMReg:0x2658]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DAT_DLY" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "DQS_DLY" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "DQS_XTR" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=No write preamble " }, { col => 3, table => 1, text => " 1=Write preamble " }, { col => 0, table => 1, text => "OEN_DLY" }, { col => 1, table => 1, text => "15:12" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "OEN_EXT" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=output enable not extended " }, { col => 3, table => 1, text => " 1=output eanble extended by one cycle ", }, { col => 0, table => 1, text => "OEN_SEL" }, { col => 1, table => 1, text => "21:20" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "ODT_DLY" }, { col => 1, table => 1, text => "27:24" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "ODT_EXT" }, { col => 1, table => 1, text => 28 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=ODT not extended " }, { col => undef, table => undef, text => " 1=ODT extended by one cycle " }, { col => undef, table => undef, text => " Channel 1's write command parameters in hclk. See MC_SEQ_WR_CTL_I1.", }, { col => undef, table => undef, text => "MC_SEQ_RD_CTL_D0_B - RW - 32 bits - [GpuF0MMReg:0x2694]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "RCV_DLY" }, { col => undef, table => undef, text => "2:0" }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=Turn on receive enable at CL-2 ", }, { col => undef, table => undef, text => " 1=Turn on receive enable at CL-1 ", }, { col => undef, table => undef, text => " 2=Turn on receive enable at CL ", }, { col => undef, table => undef, text => " 3=Turn on receive enable at CL+1 ", }, { col => undef, table => undef, text => " 4=Turn on receive enable at CL+2 ", }, { col => undef, table => undef, text => " 5=Turn on receive enable at CL+3 ", }, { col => undef, table => undef, text => " 6=Turn on receive enable at CL+4 ", }, { col => undef, table => undef, text => " 7=Turn on receive enable at CL+5 ", }, ], }, { num => 21, text => [ { col => 0, table => 0, text => "RCV_EXT" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=DQS receive enable not extended " }, { col => 3, table => 0, text => " 1=DQS receive enable extended by 1 cycle ", }, { col => 3, table => 0, text => " 2=DQS receive enable extended by 2 cycles ", }, { col => 3, table => 0, text => " 3=DQS receive enable extended by 3 cycles ", }, { col => 3, table => 0, text => " 4=DQS receive enable extended by 4 cycles ", }, { col => 3, table => 0, text => " 5=DQS receive enable extended by 5 cycles ", }, { col => 3, table => 0, text => " 6=DQS receive enable extended by 6 cycles ", }, { col => 3, table => 0, text => " 7=DQS receive enable extended by 7 cycles ", }, { col => 3, table => 0, text => " 8=DQS receive enable always on " }, { col => 0, table => 0, text => "RST_SEL" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => " 0=Reset pointers off " }, { col => 3, table => 0, text => " 1=Reset pointers on " }, { col => 3, table => 0, text => " 2=Reset pointers before read " }, { col => 3, table => 0, text => " 3=Reset pointers during refresh " }, { col => 0, table => 0, text => "RST_HLD" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable reset by 11 cycles " }, { col => 3, table => 0, text => " 1=Disable reset by 12 cycles " }, { col => 3, table => 0, text => " 2=Disable reset by 13 cycles " }, { col => 3, table => 0, text => " 3=Disable reset by 14 cycles " }, { col => 3, table => 0, text => " 4=Disable reset by 15 cycles " }, { col => 3, table => 0, text => " 5=Disable reset by 16 cycles " }, { col => 3, table => 0, text => " 6=Disable reset by 17 cycles " }, { col => 3, table => 0, text => " 7=Disable reset by 18 cycles " }, { col => 3, table => 0, text => " 8=Disable reset by 19 cycles " }, { col => 3, table => 0, text => " 9=Disable reset by 20 cycles " }, { col => 3, table => 0, text => " 10=Disable reset by 21 cycles " }, { col => 3, table => 0, text => " 11=Disable reset by 22 cycles " }, { col => 3, table => 0, text => " 12=Disable reset by 23 cycles " }, { col => 3, table => 0, text => " 13=Disable reset by 24 cycles " }, { col => 3, table => 0, text => " 14=Disable reset by 25 cycles " }, { col => 0, table => 0, text => "STR_PRE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read pre strobe " }, { col => 3, table => 0, text => " 1=Extra read pre strobe " }, { col => 0, table => 0, text => "STR_PST" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read post strobe " }, { col => 3, table => 0, text => " 1=Extra read post strobe " }, { col => 0, table => 0, text => "RBS_DLY" }, { col => 1, table => 0, text => "24:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Assert RBS valid at CL+8 " }, { col => 3, table => 0, text => " 1=Assert RBS valid at CL+9 " }, { col => 3, table => 0, text => " 2=Assert RBS valid at CL+10 " }, { col => 3, table => 0, text => " 3=Assert RBS valid at CL+11 " }, { col => 3, table => 0, text => " 4=Assert RBS valid at CL+12 " }, { col => 3, table => 0, text => " 5=Assert RBS valid at CL+13 " }, { col => 3, table => 0, text => " 6=Assert RBS valid at CL+14 " }, { col => 3, table => 0, text => " 7=Assert RBS valid at CL+15 " }, { col => 3, table => 0, text => " 8=Assert RBS valid at CL+16 " }, { col => 3, table => 0, text => " 9=Assert RBS valid at CL+17 " }, { col => 3, table => 0, text => " 10=Assert RBS valid at CL+18 " }, { col => 3, table => 0, text => " 11=Assert RBS valid at CL+19 " }, { col => 3, table => 0, text => " 12=Assert RBS valid at CL+20 " }, { col => 3, table => 0, text => " 13=Assert RBS valid at CL+21 " }, { col => 3, table => 0, text => " 14=Assert RBS valid at CL+22 " }, { col => 3, table => 0, text => " 15=Assert RBS valid at CL+23 " }, { col => 3, table => 0, text => " 16=Assert RBS valid at CL+24 " }, { col => 3, table => 0, text => " 17=Assert RBS valid at CL+25 " }, { col => undef, table => undef, text => "MC_SEQ_RD_CTL_D1_B - RW - 32 bits - [GpuF0MMReg:0x2698]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, ], }, { num => 22, text => [ { col => 0, table => 0, text => "RCV_DLY" }, { col => 1, table => 0, text => "2:0" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=Turn on receive enable at CL-2 " }, { col => 3, table => 0, text => " 1=Turn on receive enable at CL-1 " }, { col => 3, table => 0, text => " 2=Turn on receive enable at CL " }, { col => 3, table => 0, text => " 3=Turn on receive enable at CL+1 " }, { col => 3, table => 0, text => " 4=Turn on receive enable at CL+2 " }, { col => 3, table => 0, text => " 5=Turn on receive enable at CL+3 " }, { col => 3, table => 0, text => " 6=Turn on receive enable at CL+4 " }, { col => 3, table => 0, text => " 7=Turn on receive enable at CL+5 " }, { col => 0, table => 0, text => "RCV_EXT" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=DQS receive enable not extended " }, { col => 3, table => 0, text => " 1=DQS receive enable extended by 1 cycle ", }, { col => 3, table => 0, text => " 2=DQS receive enable extended by 2 cycles ", }, { col => 3, table => 0, text => " 3=DQS receive enable extended by 3 cycles ", }, { col => 3, table => 0, text => " 4=DQS receive enable extended by 4 cycles ", }, { col => 3, table => 0, text => " 5=DQS receive enable extended by 5 cycles ", }, { col => 3, table => 0, text => " 6=DQS receive enable extended by 6 cycles ", }, { col => 3, table => 0, text => " 7=DQS receive enable extended by 7 cycles ", }, { col => 3, table => 0, text => " 8=DQS receive enable always on " }, { col => 0, table => 0, text => "RST_SEL" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => " 0=Reset pointers off " }, { col => 3, table => 0, text => " 1=Reset pointers on " }, { col => 3, table => 0, text => " 2=Reset pointers before read " }, { col => 3, table => 0, text => " 3=Reset pointers during refresh " }, { col => 0, table => 0, text => "RST_HLD" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable reset by 11 cycles " }, { col => 3, table => 0, text => " 1=Disable reset by 12 cycles " }, { col => 3, table => 0, text => " 2=Disable reset by 13 cycles " }, { col => 3, table => 0, text => " 3=Disable reset by 14 cycles " }, { col => 3, table => 0, text => " 4=Disable reset by 15 cycles " }, { col => 3, table => 0, text => " 5=Disable reset by 16 cycles " }, { col => 3, table => 0, text => " 6=Disable reset by 17 cycles " }, { col => 3, table => 0, text => " 7=Disable reset by 18 cycles " }, { col => 3, table => 0, text => " 8=Disable reset by 19 cycles " }, { col => 3, table => 0, text => " 9=Disable reset by 20 cycles " }, { col => 3, table => 0, text => " 10=Disable reset by 21 cycles " }, { col => 3, table => 0, text => " 11=Disable reset by 22 cycles " }, { col => 3, table => 0, text => " 12=Disable reset by 23 cycles " }, { col => 3, table => 0, text => " 13=Disable reset by 24 cycles " }, { col => 3, table => 0, text => " 14=Disable reset by 25 cycles " }, { col => 0, table => 0, text => "STR_PRE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read pre strobe " }, { col => 3, table => 0, text => " 1=Extra read pre strobe " }, { col => 0, table => 0, text => "STR_PST" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read post strobe " }, { col => 3, table => 0, text => " 1=Extra read post strobe " }, { col => 0, table => 0, text => "RBS_DLY" }, { col => 1, table => 0, text => "24:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Assert RBS valid at CL+8 " }, { col => 3, table => 0, text => " 1=Assert RBS valid at CL+9 " }, { col => 3, table => 0, text => " 2=Assert RBS valid at CL+10 " }, { col => 3, table => 0, text => " 3=Assert RBS valid at CL+11 " }, { col => 3, table => 0, text => " 4=Assert RBS valid at CL+12 " }, { col => 3, table => 0, text => " 5=Assert RBS valid at CL+13 " }, { col => 3, table => 0, text => " 6=Assert RBS valid at CL+14 " }, { col => 3, table => 0, text => " 7=Assert RBS valid at CL+15 " }, { col => 3, table => 0, text => " 8=Assert RBS valid at CL+16 " }, { col => 3, table => 0, text => " 9=Assert RBS valid at CL+17 " }, { col => 3, table => 0, text => " 10=Assert RBS valid at CL+18 " }, { col => 3, table => 0, text => " 11=Assert RBS valid at CL+19 " }, { col => 3, table => 0, text => " 12=Assert RBS valid at CL+20 " }, { col => 3, table => 0, text => " 13=Assert RBS valid at CL+21 " }, { col => 3, table => 0, text => " 14=Assert RBS valid at CL+22 " }, { col => 3, table => 0, text => " 15=Assert RBS valid at CL+23 " }, { col => 3, table => 0, text => " 16=Assert RBS valid at CL+24 " }, { col => 3, table => 0, text => " 17=Assert RBS valid at CL+25 " }, ], }, { num => 23, text => [ { col => "heading", table => 0, text => "MC_SEQ_WR_CTL_D0_B - RW - 32 bits - [GpuF0MMReg:0x269C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DAT_DLY" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "DQS_DLY" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "DQS_XTR" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No write preamble " }, { col => 3, table => 0, text => " 1=Write preamble " }, { col => 0, table => 0, text => "OEN_DLY" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "OEN_EXT" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=output enable not extended " }, { col => 3, table => 0, text => " 1=output eanble extended by one cycle ", }, { col => 0, table => 0, text => "OEN_SEL" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "ODT_DLY" }, { col => 1, table => 0, text => "27:24" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "ODT_EXT" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=ODT not extended " }, { col => 3, table => 0, text => " 1=ODT extended by one cycle " }, { col => "heading", table => 1, text => "MC_SEQ_WR_CTL_D1_B - RW - 32 bits - [GpuF0MMReg:0x26A0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DAT_DLY" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "DQS_DLY" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "DQS_XTR" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=No write preamble " }, { col => 3, table => 1, text => " 1=Write preamble " }, { col => 0, table => 1, text => "OEN_DLY" }, { col => 1, table => 1, text => "15:12" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "OEN_EXT" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=output enable not extended " }, { col => 3, table => 1, text => " 1=output eanble extended by one cycle ", }, { col => 0, table => 1, text => "OEN_SEL" }, { col => 1, table => 1, text => "21:20" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "ODT_DLY" }, { col => 1, table => 1, text => "27:24" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "ODT_EXT" }, { col => 1, table => 1, text => 28 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=ODT not extended " }, { col => 3, table => 1, text => " 1=ODT extended by one cycle " }, { col => "heading", table => 2, text => "MC_SEQ_RD_CTL_D0_S - RW - 32 bits - [GpuF0MMReg:0x26A4]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "RCV_DLY" }, { col => 1, table => 2, text => "2:0" }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0=Turn on receive enable at CL-2 " }, { col => 3, table => 2, text => " 1=Turn on receive enable at CL-1 " }, { col => 3, table => 2, text => " 2=Turn on receive enable at CL " }, { col => 3, table => 2, text => " 3=Turn on receive enable at CL+1 " }, { col => 3, table => 2, text => " 4=Turn on receive enable at CL+2 " }, { col => 3, table => 2, text => " 5=Turn on receive enable at CL+3 " }, { col => 3, table => 2, text => " 6=Turn on receive enable at CL+4 " }, { col => 3, table => 2, text => " 7=Turn on receive enable at CL+5 " }, { col => 0, table => 2, text => "RCV_EXT" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0=DQS receive enable not extended " }, { col => 3, table => 2, text => " 1=DQS receive enable extended by 1 cycle ", }, { col => 3, table => 2, text => " 2=DQS receive enable extended by 2 cycles ", }, { col => 3, table => 2, text => " 3=DQS receive enable extended by 3 cycles ", }, { col => 3, table => 2, text => " 4=DQS receive enable extended by 4 cycles ", }, { col => 3, table => 2, text => " 5=DQS receive enable extended by 5 cycles ", }, { col => 3, table => 2, text => " 6=DQS receive enable extended by 6 cycles ", }, { col => 3, table => 2, text => " 7=DQS receive enable extended by 7 cycles ", }, { col => 3, table => 2, text => " 8=DQS receive enable always on " }, ], }, { num => 24, text => [ { col => 0, table => 0, text => "RST_SEL" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => " 0=Reset pointers off " }, { col => 3, table => 0, text => " 1=Reset pointers on " }, { col => 3, table => 0, text => " 2=Reset pointers before read " }, { col => 3, table => 0, text => " 3=Reset pointers during refresh " }, { col => 0, table => 0, text => "RST_HLD" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable reset by 11 cycles " }, { col => 3, table => 0, text => " 1=Disable reset by 12 cycles " }, { col => 3, table => 0, text => " 2=Disable reset by 13 cycles " }, { col => 3, table => 0, text => " 3=Disable reset by 14 cycles " }, { col => 3, table => 0, text => " 4=Disable reset by 15 cycles " }, { col => 3, table => 0, text => " 5=Disable reset by 16 cycles " }, { col => 3, table => 0, text => " 6=Disable reset by 17 cycles " }, { col => 3, table => 0, text => " 7=Disable reset by 18 cycles " }, { col => 3, table => 0, text => " 8=Disable reset by 19 cycles " }, { col => 3, table => 0, text => " 9=Disable reset by 20 cycles " }, { col => 3, table => 0, text => " 10=Disable reset by 21 cycles " }, { col => 3, table => 0, text => " 11=Disable reset by 22 cycles " }, { col => 3, table => 0, text => " 12=Disable reset by 23 cycles " }, { col => 3, table => 0, text => " 13=Disable reset by 24 cycles " }, { col => 3, table => 0, text => " 14=Disable reset by 25 cycles " }, { col => 0, table => 0, text => "STR_PRE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read pre strobe " }, { col => 3, table => 0, text => " 1=Extra read pre strobe " }, { col => 0, table => 0, text => "STR_PST" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read post strobe " }, { col => 3, table => 0, text => " 1=Extra read post strobe " }, { col => 0, table => 0, text => "RBS_DLY" }, { col => 1, table => 0, text => "24:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Assert RBS valid at CL+8 " }, { col => 3, table => 0, text => " 1=Assert RBS valid at CL+9 " }, { col => 3, table => 0, text => " 2=Assert RBS valid at CL+10 " }, { col => 3, table => 0, text => " 3=Assert RBS valid at CL+11 " }, { col => 3, table => 0, text => " 4=Assert RBS valid at CL+12 " }, { col => 3, table => 0, text => " 5=Assert RBS valid at CL+13 " }, { col => 3, table => 0, text => " 6=Assert RBS valid at CL+14 " }, { col => 3, table => 0, text => " 7=Assert RBS valid at CL+15 " }, { col => 3, table => 0, text => " 8=Assert RBS valid at CL+16 " }, { col => 3, table => 0, text => " 9=Assert RBS valid at CL+17 " }, { col => 3, table => 0, text => " 10=Assert RBS valid at CL+18 " }, { col => 3, table => 0, text => " 11=Assert RBS valid at CL+19 " }, { col => 3, table => 0, text => " 12=Assert RBS valid at CL+20 " }, { col => 3, table => 0, text => " 13=Assert RBS valid at CL+21 " }, { col => 3, table => 0, text => " 14=Assert RBS valid at CL+22 " }, { col => 3, table => 0, text => " 15=Assert RBS valid at CL+23 " }, { col => 3, table => 0, text => " 16=Assert RBS valid at CL+24 " }, { col => 3, table => 0, text => " 17=Assert RBS valid at CL+25 " }, { col => undef, table => undef, text => "MC_SEQ_RD_CTL_D1_S - RW - 32 bits - [GpuF0MMReg:0x26A8]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "RCV_DLY" }, { col => undef, table => undef, text => "2:0" }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=Turn on receive enable at CL-2 ", }, { col => undef, table => undef, text => " 1=Turn on receive enable at CL-1 ", }, { col => undef, table => undef, text => " 2=Turn on receive enable at CL ", }, { col => undef, table => undef, text => " 3=Turn on receive enable at CL+1 ", }, { col => undef, table => undef, text => " 4=Turn on receive enable at CL+2 ", }, { col => undef, table => undef, text => " 5=Turn on receive enable at CL+3 ", }, { col => undef, table => undef, text => " 6=Turn on receive enable at CL+4 ", }, { col => undef, table => undef, text => " 7=Turn on receive enable at CL+5 ", }, ], }, { num => 25, text => [ { col => 0, table => 0, text => "RCV_EXT" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=DQS receive enable not extended " }, { col => 3, table => 0, text => " 1=DQS receive enable extended by 1 cycle ", }, { col => 3, table => 0, text => " 2=DQS receive enable extended by 2 cycles ", }, { col => 3, table => 0, text => " 3=DQS receive enable extended by 3 cycles ", }, { col => 3, table => 0, text => " 4=DQS receive enable extended by 4 cycles ", }, { col => 3, table => 0, text => " 5=DQS receive enable extended by 5 cycles ", }, { col => 3, table => 0, text => " 6=DQS receive enable extended by 6 cycles ", }, { col => 3, table => 0, text => " 7=DQS receive enable extended by 7 cycles ", }, { col => 3, table => 0, text => " 8=DQS receive enable always on " }, { col => 0, table => 0, text => "RST_SEL" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => " 0=Reset pointers off " }, { col => 3, table => 0, text => " 1=Reset pointers on " }, { col => 3, table => 0, text => " 2=Reset pointers before read " }, { col => 3, table => 0, text => " 3=Reset pointers during refresh " }, { col => 0, table => 0, text => "RST_HLD" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable reset by 11 cycles " }, { col => 3, table => 0, text => " 1=Disable reset by 12 cycles " }, { col => 3, table => 0, text => " 2=Disable reset by 13 cycles " }, { col => 3, table => 0, text => " 3=Disable reset by 14 cycles " }, { col => 3, table => 0, text => " 4=Disable reset by 15 cycles " }, { col => 3, table => 0, text => " 5=Disable reset by 16 cycles " }, { col => 3, table => 0, text => " 6=Disable reset by 17 cycles " }, { col => 3, table => 0, text => " 7=Disable reset by 18 cycles " }, { col => 3, table => 0, text => " 8=Disable reset by 19 cycles " }, { col => 3, table => 0, text => " 9=Disable reset by 20 cycles " }, { col => 3, table => 0, text => " 10=Disable reset by 21 cycles " }, { col => 3, table => 0, text => " 11=Disable reset by 22 cycles " }, { col => 3, table => 0, text => " 12=Disable reset by 23 cycles " }, { col => 3, table => 0, text => " 13=Disable reset by 24 cycles " }, { col => 3, table => 0, text => " 14=Disable reset by 25 cycles " }, { col => 0, table => 0, text => "STR_PRE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read pre strobe " }, { col => 3, table => 0, text => " 1=Extra read pre strobe " }, { col => 0, table => 0, text => "STR_PST" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read post strobe " }, { col => 3, table => 0, text => " 1=Extra read post strobe " }, { col => 0, table => 0, text => "RBS_DLY" }, { col => 1, table => 0, text => "24:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Assert RBS valid at CL+8 " }, { col => 3, table => 0, text => " 1=Assert RBS valid at CL+9 " }, { col => 3, table => 0, text => " 2=Assert RBS valid at CL+10 " }, { col => 3, table => 0, text => " 3=Assert RBS valid at CL+11 " }, { col => 3, table => 0, text => " 4=Assert RBS valid at CL+12 " }, { col => 3, table => 0, text => " 5=Assert RBS valid at CL+13 " }, { col => 3, table => 0, text => " 6=Assert RBS valid at CL+14 " }, { col => 3, table => 0, text => " 7=Assert RBS valid at CL+15 " }, { col => 3, table => 0, text => " 8=Assert RBS valid at CL+16 " }, { col => 3, table => 0, text => " 9=Assert RBS valid at CL+17 " }, { col => 3, table => 0, text => " 10=Assert RBS valid at CL+18 " }, { col => 3, table => 0, text => " 11=Assert RBS valid at CL+19 " }, { col => 3, table => 0, text => " 12=Assert RBS valid at CL+20 " }, { col => 3, table => 0, text => " 13=Assert RBS valid at CL+21 " }, { col => 3, table => 0, text => " 14=Assert RBS valid at CL+22 " }, { col => 3, table => 0, text => " 15=Assert RBS valid at CL+23 " }, { col => 3, table => 0, text => " 16=Assert RBS valid at CL+24 " }, { col => 3, table => 0, text => " 17=Assert RBS valid at CL+25 " }, { col => "heading", table => 1, text => "MC_SEQ_WR_CTL_D0_S - RW - 32 bits - [GpuF0MMReg:0x26AC]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DAT_DLY" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "DQS_DLY" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x3" }, ], }, { num => 26, text => [ { col => 0, table => 0, text => "DQS_XTR" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No write preamble " }, { col => 3, table => 0, text => " 1=Write preamble " }, { col => 0, table => 0, text => "OEN_DLY" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "OEN_EXT" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=output enable not extended " }, { col => 3, table => 0, text => " 1=output eanble extended by one cycle ", }, { col => 0, table => 0, text => "OEN_SEL" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "ODT_DLY" }, { col => 1, table => 0, text => "27:24" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "ODT_EXT" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=ODT not extended " }, { col => 3, table => 0, text => " 1=ODT extended by one cycle " }, { col => "heading", table => 1, text => "MC_SEQ_WR_CTL_D1_S - RW - 32 bits - [GpuF0MMReg:0x26B0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DAT_DLY" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "DQS_DLY" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "DQS_XTR" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=No write preamble " }, { col => 3, table => 1, text => " 1=Write preamble " }, { col => 0, table => 1, text => "OEN_DLY" }, { col => 1, table => 1, text => "15:12" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "OEN_EXT" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=output enable not extended " }, { col => 3, table => 1, text => " 1=output eanble extended by one cycle ", }, { col => 0, table => 1, text => "OEN_SEL" }, { col => 1, table => 1, text => "21:20" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "ODT_DLY" }, { col => 1, table => 1, text => "27:24" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "ODT_EXT" }, { col => 1, table => 1, text => 28 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=ODT not extended " }, { col => 3, table => 1, text => " 1=ODT extended by one cycle " }, { col => "heading", table => 2, text => "MC_SEQ_RD_CTL_D0_C - RW - 32 bits - [GpuF0MMReg:0x26B4]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "RCV_DLY" }, { col => 1, table => 2, text => "2:0" }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0=Turn on receive enable at CL-2 " }, { col => 3, table => 2, text => " 1=Turn on receive enable at CL-1 " }, { col => 3, table => 2, text => " 2=Turn on receive enable at CL " }, { col => 3, table => 2, text => " 3=Turn on receive enable at CL+1 " }, { col => 3, table => 2, text => " 4=Turn on receive enable at CL+2 " }, { col => 3, table => 2, text => " 5=Turn on receive enable at CL+3 " }, { col => 3, table => 2, text => " 6=Turn on receive enable at CL+4 " }, { col => 3, table => 2, text => " 7=Turn on receive enable at CL+5 " }, { col => 0, table => 2, text => "RCV_EXT" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0=DQS receive enable not extended " }, { col => 3, table => 2, text => " 1=DQS receive enable extended by 1 cycle ", }, { col => 3, table => 2, text => " 2=DQS receive enable extended by 2 cycles ", }, { col => 3, table => 2, text => " 3=DQS receive enable extended by 3 cycles ", }, { col => 3, table => 2, text => " 4=DQS receive enable extended by 4 cycles ", }, { col => 3, table => 2, text => " 5=DQS receive enable extended by 5 cycles ", }, { col => 3, table => 2, text => " 6=DQS receive enable extended by 6 cycles ", }, { col => 3, table => 2, text => " 7=DQS receive enable extended by 7 cycles ", }, { col => 3, table => 2, text => " 8=DQS receive enable always on " }, { col => 0, table => 2, text => "RST_SEL" }, { col => 1, table => 2, text => "9:8" }, { col => 2, table => 2, text => "0x2" }, { col => 3, table => 2, text => " 0=Reset pointers off " }, { col => 3, table => 2, text => " 1=Reset pointers on " }, { col => 3, table => 2, text => " 2=Reset pointers before read " }, { col => 3, table => 2, text => " 3=Reset pointers during refresh " }, ], }, { num => 27, text => [ { col => 0, table => 0, text => "RST_HLD" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable reset by 11 cycles " }, { col => 3, table => 0, text => " 1=Disable reset by 12 cycles " }, { col => 3, table => 0, text => " 2=Disable reset by 13 cycles " }, { col => 3, table => 0, text => " 3=Disable reset by 14 cycles " }, { col => 3, table => 0, text => " 4=Disable reset by 15 cycles " }, { col => 3, table => 0, text => " 5=Disable reset by 16 cycles " }, { col => 3, table => 0, text => " 6=Disable reset by 17 cycles " }, { col => 3, table => 0, text => " 7=Disable reset by 18 cycles " }, { col => 3, table => 0, text => " 8=Disable reset by 19 cycles " }, { col => 3, table => 0, text => " 9=Disable reset by 20 cycles " }, { col => 3, table => 0, text => " 10=Disable reset by 21 cycles " }, { col => 3, table => 0, text => " 11=Disable reset by 22 cycles " }, { col => 3, table => 0, text => " 12=Disable reset by 23 cycles " }, { col => 3, table => 0, text => " 13=Disable reset by 24 cycles " }, { col => 3, table => 0, text => " 14=Disable reset by 25 cycles " }, { col => 0, table => 0, text => "STR_PRE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read pre strobe " }, { col => 3, table => 0, text => " 1=Extra read pre strobe " }, { col => 0, table => 0, text => "STR_PST" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read post strobe " }, { col => 3, table => 0, text => " 1=Extra read post strobe " }, { col => 0, table => 0, text => "RBS_DLY" }, { col => 1, table => 0, text => "24:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Assert RBS valid at CL+8 " }, { col => 3, table => 0, text => " 1=Assert RBS valid at CL+9 " }, { col => 3, table => 0, text => " 2=Assert RBS valid at CL+10 " }, { col => 3, table => 0, text => " 3=Assert RBS valid at CL+11 " }, { col => 3, table => 0, text => " 4=Assert RBS valid at CL+12 " }, { col => 3, table => 0, text => " 5=Assert RBS valid at CL+13 " }, { col => 3, table => 0, text => " 6=Assert RBS valid at CL+14 " }, { col => 3, table => 0, text => " 7=Assert RBS valid at CL+15 " }, { col => 3, table => 0, text => " 8=Assert RBS valid at CL+16 " }, { col => 3, table => 0, text => " 9=Assert RBS valid at CL+17 " }, { col => 3, table => 0, text => " 10=Assert RBS valid at CL+18 " }, { col => 3, table => 0, text => " 11=Assert RBS valid at CL+19 " }, { col => 3, table => 0, text => " 12=Assert RBS valid at CL+20 " }, { col => 3, table => 0, text => " 13=Assert RBS valid at CL+21 " }, { col => 3, table => 0, text => " 14=Assert RBS valid at CL+22 " }, { col => 3, table => 0, text => " 15=Assert RBS valid at CL+23 " }, { col => 3, table => 0, text => " 16=Assert RBS valid at CL+24 " }, { col => 3, table => 0, text => " 17=Assert RBS valid at CL+25 " }, { col => undef, table => undef, text => "MC_SEQ_RD_CTL_D1_C - RW - 32 bits - [GpuF0MMReg:0x26B8]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "RCV_DLY" }, { col => undef, table => undef, text => "2:0" }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=Turn on receive enable at CL-2 ", }, { col => undef, table => undef, text => " 1=Turn on receive enable at CL-1 ", }, { col => undef, table => undef, text => " 2=Turn on receive enable at CL ", }, { col => undef, table => undef, text => " 3=Turn on receive enable at CL+1 ", }, { col => undef, table => undef, text => " 4=Turn on receive enable at CL+2 ", }, { col => undef, table => undef, text => " 5=Turn on receive enable at CL+3 ", }, { col => undef, table => undef, text => " 6=Turn on receive enable at CL+4 ", }, { col => undef, table => undef, text => " 7=Turn on receive enable at CL+5 ", }, ], }, { num => 28, text => [ { col => 0, table => 0, text => "RCV_EXT" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=DQS receive enable not extended " }, { col => 3, table => 0, text => " 1=DQS receive enable extended by 1 cycle ", }, { col => 3, table => 0, text => " 2=DQS receive enable extended by 2 cycles ", }, { col => 3, table => 0, text => " 3=DQS receive enable extended by 3 cycles ", }, { col => 3, table => 0, text => " 4=DQS receive enable extended by 4 cycles ", }, { col => 3, table => 0, text => " 5=DQS receive enable extended by 5 cycles ", }, { col => 3, table => 0, text => " 6=DQS receive enable extended by 6 cycles ", }, { col => 3, table => 0, text => " 7=DQS receive enable extended by 7 cycles ", }, { col => 3, table => 0, text => " 8=DQS receive enable always on " }, { col => 0, table => 0, text => "RST_SEL" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => " 0=Reset pointers off " }, { col => 3, table => 0, text => " 1=Reset pointers on " }, { col => 3, table => 0, text => " 2=Reset pointers before read " }, { col => 3, table => 0, text => " 3=Reset pointers during refresh " }, { col => 0, table => 0, text => "RST_HLD" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable reset by 11 cycles " }, { col => 3, table => 0, text => " 1=Disable reset by 12 cycles " }, { col => 3, table => 0, text => " 2=Disable reset by 13 cycles " }, { col => 3, table => 0, text => " 3=Disable reset by 14 cycles " }, { col => 3, table => 0, text => " 4=Disable reset by 15 cycles " }, { col => 3, table => 0, text => " 5=Disable reset by 16 cycles " }, { col => 3, table => 0, text => " 6=Disable reset by 17 cycles " }, { col => 3, table => 0, text => " 7=Disable reset by 18 cycles " }, { col => 3, table => 0, text => " 8=Disable reset by 19 cycles " }, { col => 3, table => 0, text => " 9=Disable reset by 20 cycles " }, { col => 3, table => 0, text => " 10=Disable reset by 21 cycles " }, { col => 3, table => 0, text => " 11=Disable reset by 22 cycles " }, { col => 3, table => 0, text => " 12=Disable reset by 23 cycles " }, { col => 3, table => 0, text => " 13=Disable reset by 24 cycles " }, { col => 3, table => 0, text => " 14=Disable reset by 25 cycles " }, { col => 0, table => 0, text => "STR_PRE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read pre strobe " }, { col => 3, table => 0, text => " 1=Extra read pre strobe " }, { col => 0, table => 0, text => "STR_PST" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read post strobe " }, { col => 3, table => 0, text => " 1=Extra read post strobe " }, { col => 0, table => 0, text => "RBS_DLY" }, { col => 1, table => 0, text => "24:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Assert RBS valid at CL+8 " }, { col => 3, table => 0, text => " 1=Assert RBS valid at CL+9 " }, { col => 3, table => 0, text => " 2=Assert RBS valid at CL+10 " }, { col => 3, table => 0, text => " 3=Assert RBS valid at CL+11 " }, { col => 3, table => 0, text => " 4=Assert RBS valid at CL+12 " }, { col => 3, table => 0, text => " 5=Assert RBS valid at CL+13 " }, { col => 3, table => 0, text => " 6=Assert RBS valid at CL+14 " }, { col => 3, table => 0, text => " 7=Assert RBS valid at CL+15 " }, { col => 3, table => 0, text => " 8=Assert RBS valid at CL+16 " }, { col => 3, table => 0, text => " 9=Assert RBS valid at CL+17 " }, { col => 3, table => 0, text => " 10=Assert RBS valid at CL+18 " }, { col => 3, table => 0, text => " 11=Assert RBS valid at CL+19 " }, { col => 3, table => 0, text => " 12=Assert RBS valid at CL+20 " }, { col => 3, table => 0, text => " 13=Assert RBS valid at CL+21 " }, { col => 3, table => 0, text => " 14=Assert RBS valid at CL+22 " }, { col => 3, table => 0, text => " 15=Assert RBS valid at CL+23 " }, { col => 3, table => 0, text => " 16=Assert RBS valid at CL+24 " }, { col => 3, table => 0, text => " 17=Assert RBS valid at CL+25 " }, { col => undef, table => undef, text => "MC_SEQ_WR_CTL_D0_C - RW - 32 bits - [GpuF0MMReg:0x26BC]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DAT_DLY" }, { col => undef, table => undef, text => "3:0" }, { col => undef, table => undef, text => "0x3" }, { col => undef, table => undef, text => "DQS_DLY" }, { col => undef, table => undef, text => "7:4" }, { col => undef, table => undef, text => "0x3" }, { col => undef, table => undef, text => "DQS_XTR" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=No write preamble " }, { col => undef, table => undef, text => " 1=Write preamble " }, ], }, { num => 29, text => [ { col => undef, table => undef, text => "OEN_DLY" }, { col => undef, table => undef, text => "15:12" }, { col => undef, table => undef, text => "0x3" }, { col => undef, table => undef, text => "OEN_EXT" }, { col => undef, table => undef, text => 16 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=output enable not extended ", }, { col => undef, table => undef, text => " 1=output eanble extended by one cycle ", }, { col => undef, table => undef, text => "OEN_SEL" }, { col => undef, table => undef, text => "21:20" }, { col => undef, table => undef, text => "0x3" }, { col => undef, table => undef, text => "ODT_DLY" }, { col => undef, table => undef, text => "27:24" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "ODT_EXT" }, { col => undef, table => undef, text => 28 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=ODT not extended " }, { col => undef, table => undef, text => " 1=ODT extended by one cycle " }, { col => "heading", table => 0, text => "MC_SEQ_WR_CTL_D1_C - RW - 32 bits - [GpuF0MMReg:0x26C0]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DAT_DLY" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "DQS_DLY" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "DQS_XTR" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No write preamble " }, { col => 3, table => 0, text => " 1=Write preamble " }, { col => 0, table => 0, text => "OEN_DLY" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "OEN_EXT" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=output enable not extended " }, { col => 3, table => 0, text => " 1=output eanble extended by one cycle ", }, { col => 0, table => 0, text => "OEN_SEL" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "ODT_DLY" }, { col => 1, table => 0, text => "27:24" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "ODT_EXT" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=ODT not extended " }, { col => 3, table => 0, text => " 1=ODT extended by one cycle " }, { col => "heading", table => 1, text => "MC_SEQ_IO_CTL_D0 - RW - 32 bits - [GpuF0MMReg:0x265C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "ADR_DLY" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Delays address output by half a hclk.", }, { col => 0, table => 1, text => "CMD_DLY" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Delays command output by half a hclk.", }, { col => 0, table => 1, text => "CKN_TRI" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Turns off negative clock manually.", }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=Tristate " }, { col => 0, table => 1, text => "CKP_TRI" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Turns off positive clock manually.", }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=Tristate " }, { col => 0, table => 1, text => "MIO_TRI" }, { col => 1, table => 1, text => 6 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Turns off address and command manually.", }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=Tristate " }, { col => 0, table => 1, text => "CKE_BIT" }, { col => 1, table => 1, text => 7 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Bypass value for clock enable.", }, { col => 0, table => 1, text => "CKE_SEL" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " Selects clock enable bypass value.", }, { col => 3, table => 1, text => " 0=Normal CKE " }, { col => 3, table => 1, text => " 1=Set CKE bit " }, { col => 0, table => 1, text => "STRD2" }, { col => 1, table => 1, text => 9 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Turn off reserved figures " }, { col => undef, table => undef, text => " 1=Turn on reserved figures " }, { col => undef, table => undef, text => " Channel 0's misc. control parameters.", }, { col => "heading", table => 2, text => "MC_SEQ_IO_CTL_D1 - RW - 32 bits - [GpuF0MMReg:0x2660]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "ADR_DLY" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "CMD_DLY" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, ], }, { num => 30, text => [ { col => 0, table => 0, text => "CKN_TRI" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Tristate " }, { col => 0, table => 0, text => "CKP_TRI" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Tristate " }, { col => 0, table => 0, text => "MIO_TRI" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Tristate " }, { col => 0, table => 0, text => "CKE_BIT" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "CKE_SEL" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=Normal CKE " }, { col => 3, table => 0, text => " 1=Set CKE bit " }, { col => 0, table => 0, text => "STRD2" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Turn off reserved figures " }, { col => undef, table => undef, text => " 1=Turn on reserved figures " }, { col => undef, table => undef, text => " Channel 1's misc. control parameters. See MC_SEQ_IO_CTL_I0.", }, { col => "heading", table => 1, text => "MC_SEQ_IO_CTL_UNUSED - RW - 32 bits - [GpuF0MMReg:0x2898]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CKN_TRI" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=Tristate " }, { col => 0, table => 1, text => "CKP_TRI" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=Tristate " }, { col => 0, table => 1, text => "MIO_TRI" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=Tristate " }, { col => 0, table => 1, text => "DAT_TRI" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=Tristate " }, { col => 0, table => 1, text => "STRD2" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Turn off reserved figures " }, { col => undef, table => undef, text => " 1=Turn on reserved figures " }, { col => undef, table => undef, text => " " }, { col => undef, table => undef, text => "Unused channel misc. control parameters. This is intended for the second 64-bit IO. ", }, { col => "heading", table => 2, text => "MC_SEQ_NPL_CTL_D0 - RW - 32 bits - [GpuF0MMReg:0x2664]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "LD_INIT" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " NPL FIFO's pointer offset." }, { col => 0, table => 2, text => "SYC_SEL" }, { col => 1, table => 2, text => "5:4" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " Selects mclk/yclk synchronization mode.", }, { col => 3, table => 2, text => " 0=mclk/yclk sync off " }, { col => 3, table => 2, text => " 1=mclk/yclk sync on " }, { col => 3, table => 2, text => " 2=mclk/yclk sync during refresh " }, { col => 3, table => 2, text => " 3=periodically turn on mclk/yclk sync ", }, { col => 0, table => 2, text => "SYC_IDLE_CNT" }, { col => 1, table => 2, text => "31:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " number of cycles a mclk/yclk sync will be ", }, { col => undef, table => undef, text => "forced " }, { col => undef, table => undef, text => " Channel 0's NPL control parameters.", }, { col => undef, table => undef, text => "MC_SEQ_NPL_CTL_D1 - RW - 32 bits - [GpuF0MMReg:0x2668]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "LD_INIT" }, { col => undef, table => undef, text => "1:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "SYC_SEL" }, { col => undef, table => undef, text => "5:4" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " Selects mclk/yclk synchronization mode. The value ", }, { col => undef, table => undef, text => "should be same as MC_SEQ_NPL_CTL_D0 for 32bit mode", }, { col => undef, table => undef, text => " 0=mclk/yclk sync off " }, { col => undef, table => undef, text => " 1=mclk/yclk sync on " }, { col => undef, table => undef, text => " 2=mclk/yclk sync during refresh ", }, { col => undef, table => undef, text => " 3=periodically turn on mclk/yclk sync ", }, ], }, { num => 31, text => [ { col => 0, table => 0, text => "SYC_IDLE_CNT" }, { col => 1, table => 0, text => "31:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " " }, { col => 3, table => 0, text => "number of cycles a mclk/yclk sync will be ", }, { col => 3, table => 0, text => "forced. The value should be same as " }, { col => undef, table => undef, text => "MC_SEQ_NPL_CTL_D0 for 32bit mode ", }, { col => undef, table => undef, text => " Channel 1's NPL control parameters. See MC_SEQ_NPL_CTL_I0.", }, { col => "heading", table => 1, text => "MC_IO_PAD_CNTL_D0 - RW - 32 bits - [GpuF0MMReg:0x27F0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DELAY_MASTER_SYNC" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "For 32bit mode, this value should be same as ", }, { col => 3, table => 1, text => "MC_IO_PAD_CNTL_D1" }, { col => 0, table => 1, text => "DIFF_STR" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Strobe single ended " }, { col => 3, table => 1, text => " 1=Strobe differential " }, { col => 0, table => 1, text => "UNI_STR" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Bidirectional strobes " }, { col => undef, table => undef, text => " 1=Unidirectional strobes " }, { col => undef, table => undef, text => "General Pad control" }, { col => "heading", table => 2, text => "MC_IO_PAD_CNTL_D1 - RW - 32 bits - [GpuF0MMReg:0x27F4]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DELAY_MASTER_SYNC" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DIFF_STR" }, { col => 1, table => 2, text => 2 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Strobe single ended " }, { col => 3, table => 2, text => " 1=Strobe differential " }, { col => 0, table => 2, text => "UNI_STR" }, { col => 1, table => 2, text => 3 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Bidirectional strobes " }, { col => 3, table => 2, text => " 1=Unidirectional strobes " }, { col => "heading", table => 3, text => "MC_SEQ_CK_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x266C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "NMOS_PD" }, { col => 1, table => 3, text => "1:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_H" }, { col => 1, table => 3, text => "7:4" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_H" }, { col => 1, table => 3, text => "11:8" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "USE_CAL_STR" }, { col => 1, table => 3, text => 12 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=Ignore cal ctl str " }, { col => 3, table => 3, text => " 1=Use cal ctl str " }, { col => 0, table => 3, text => "LOAD_STR" }, { col => 1, table => 3, text => 13 }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_V" }, { col => 1, table => 3, text => "19:16" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_V" }, { col => 1, table => 3, text => "23:20" }, { col => 2, table => 3, text => "0x0" }, { col => "heading", table => 4, text => "MC_SEQ_CK_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2670]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "NMOS_PD" }, { col => 1, table => 4, text => "1:0" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "PSTR_OFF_H" }, { col => 1, table => 4, text => "7:4" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "NSTR_OFF_H" }, { col => 1, table => 4, text => "11:8" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "USE_CAL_STR" }, { col => 1, table => 4, text => 12 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => " 0=Ignore cal ctl str " }, { col => 3, table => 4, text => " 1=Use cal ctl str " }, { col => 0, table => 4, text => "LOAD_STR" }, { col => 1, table => 4, text => 13 }, { col => 2, table => 4, text => "0x0" }, ], }, { num => 32, text => [ { col => 0, table => 0, text => "PSTR_OFF_V" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NSTR_OFF_V" }, { col => 1, table => 0, text => "23:20" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_SEQ_CMD_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2674]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "NMOS_PD" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PSTR_OFF_H" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NSTR_OFF_H" }, { col => 1, table => 1, text => "11:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "USE_CAL_STR" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Ignore cal ctl str " }, { col => 3, table => 1, text => " 1=Use cal ctl str " }, { col => 0, table => 1, text => "LOAD_STR" }, { col => 1, table => 1, text => 13 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PSTR_OFF_V" }, { col => 1, table => 1, text => "19:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NSTR_OFF_V" }, { col => 1, table => 1, text => "23:20" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_SEQ_CMD_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2678]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "NMOS_PD" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PSTR_OFF_H" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NSTR_OFF_H" }, { col => 1, table => 2, text => "11:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "USE_CAL_STR" }, { col => 1, table => 2, text => 12 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Ignore cal ctl str " }, { col => 3, table => 2, text => " 1=Use cal ctl str " }, { col => 0, table => 2, text => "LOAD_STR" }, { col => 1, table => 2, text => 13 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PSTR_OFF_V" }, { col => 1, table => 2, text => "19:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NSTR_OFF_V" }, { col => 1, table => 2, text => "23:20" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_SEQ_DQ_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x267C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "NMOS_PD" }, { col => 1, table => 3, text => "1:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_H" }, { col => 1, table => 3, text => "7:4" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_H" }, { col => 1, table => 3, text => "11:8" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "USE_CAL_STR" }, { col => 1, table => 3, text => 12 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=Ignore cal ctl str " }, { col => 3, table => 3, text => " 1=Use cal ctl str " }, { col => 0, table => 3, text => "LOAD_STR" }, { col => 1, table => 3, text => 13 }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_V" }, { col => 1, table => 3, text => "19:16" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_V" }, { col => 1, table => 3, text => "23:20" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "MC_SEQ_DQ_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2680]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "NMOS_PD" }, { col => undef, table => undef, text => "1:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "PSTR_OFF_H" }, { col => undef, table => undef, text => "7:4" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "NSTR_OFF_H" }, { col => undef, table => undef, text => "11:8" }, { col => undef, table => undef, text => "0x0" }, ], }, { num => 33, text => [ { col => 0, table => 0, text => "USE_CAL_STR" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Ignore cal ctl str " }, { col => 3, table => 0, text => " 1=Use cal ctl str " }, { col => 0, table => 0, text => "LOAD_STR" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PSTR_OFF_V" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NSTR_OFF_V" }, { col => 1, table => 0, text => "23:20" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_SEQ_QS_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2684]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "NMOS_PD" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PSTR_OFF_H" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NSTR_OFF_H" }, { col => 1, table => 1, text => "11:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "USE_CAL_STR" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Ignore cal ctl str " }, { col => 3, table => 1, text => " 1=Use cal ctl str " }, { col => 0, table => 1, text => "LOAD_STR" }, { col => 1, table => 1, text => 13 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PSTR_OFF_V" }, { col => 1, table => 1, text => "19:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NSTR_OFF_V" }, { col => 1, table => 1, text => "23:20" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_SEQ_QS_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2688]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "NMOS_PD" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PSTR_OFF_H" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NSTR_OFF_H" }, { col => 1, table => 2, text => "11:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "USE_CAL_STR" }, { col => 1, table => 2, text => 12 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Ignore cal ctl str " }, { col => 3, table => 2, text => " 1=Use cal ctl str " }, { col => 0, table => 2, text => "LOAD_STR" }, { col => 1, table => 2, text => 13 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PSTR_OFF_V" }, { col => 1, table => 2, text => "19:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NSTR_OFF_V" }, { col => 1, table => 2, text => "23:20" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_SEQ_A_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x268C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "NMOS_PD" }, { col => 1, table => 3, text => "1:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_H" }, { col => 1, table => 3, text => "7:4" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_H" }, { col => 1, table => 3, text => "11:8" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "USE_CAL_STR" }, { col => 1, table => 3, text => 12 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=Ignore cal ctl str " }, { col => 3, table => 3, text => " 1=Use cal ctl str " }, { col => 0, table => 3, text => "LOAD_STR" }, { col => 1, table => 3, text => 13 }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_V" }, { col => 1, table => 3, text => "19:16" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_V" }, { col => 1, table => 3, text => "23:20" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "MC_SEQ_A_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2690]", }, ], }, { num => 34, text => [ { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "NMOS_PD" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PSTR_OFF_H" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NSTR_OFF_H" }, { col => 1, table => 0, text => "11:8" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "USE_CAL_STR" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Ignore cal ctl str " }, { col => 3, table => 0, text => " 1=Use cal ctl str " }, { col => 0, table => 0, text => "LOAD_STR" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PSTR_OFF_V" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NSTR_OFF_V" }, { col => 1, table => 0, text => "23:20" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2704]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DELAY_DATA_SYNC" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay data sync " }, { col => 3, table => 1, text => " 1=delay data sync by 1 yclk " }, { col => 0, table => 1, text => "DELAY_STR_SYNC" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay strobe sync " }, { col => 3, table => 1, text => " 1=delay strobe sync by 1 yclk " }, { col => 0, table => 1, text => "DELAY_CLK_SYNC" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay clk sync " }, { col => 3, table => 1, text => " 1=delay clk sync by 1 yclk " }, { col => 0, table => 1, text => "DELAY_CMD_SYNC" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay cmd sync " }, { col => 3, table => 1, text => " 1=delay cmd sync by 1 yclk " }, { col => 0, table => 1, text => "DELAY_ADR_SYNC" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay adr sync " }, { col => 3, table => 1, text => " 1=delay adr sync by 1 yclk " }, { col => 0, table => 1, text => "MEM_FALL_OUT_DATA" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Data out on YCLK rise " }, { col => 3, table => 1, text => " 1=Data out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 1, text => "MEM_FALL_OUT_STR" }, { col => 1, table => 1, text => 6 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Strobe out on YCLK rise " }, { col => 3, table => 1, text => " 1=Strobe out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 1, text => "MEM_FALL_OUT_CLK" }, { col => 1, table => 1, text => 7 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Clk out on YCLK rise " }, { col => 3, table => 1, text => " 1=Clk out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 1, text => "MEM_FALL_OUT_CMD" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Command out on YCLK rise " }, { col => 3, table => 1, text => " 1=Command out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 1, text => "MEM_FALL_OUT_ADR" }, { col => 1, table => 1, text => 9 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Address out on YCLK rise " }, { col => 3, table => 1, text => " 1=Address out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 1, text => "FORCE_EN_RD_STR" }, { col => 1, table => 1, text => 10 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Read strb enabled by MC " }, { col => 3, table => 1, text => " 1=Always enable read strb " }, { col => 0, table => 1, text => "EN_RD_STR_DLY" }, { col => 1, table => 1, text => 11 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=count rising edge " }, { col => 3, table => 1, text => " 1=count falling edge " }, { col => 0, table => 1, text => "DISABLE_CMD" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Drive command " }, { col => 3, table => 1, text => " 1=Disable command " }, { col => 0, table => 1, text => "DISABLE_ADR" }, { col => 1, table => 1, text => 13 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Drive address " }, { col => 3, table => 1, text => " 1=Disable address " }, { col => 0, table => 1, text => "VREFI_EN" }, { col => 1, table => 1, text => 14 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=VREFI disable " }, { col => 3, table => 1, text => " 1=VREFI enable " }, { col => 0, table => 1, text => "VREFI_SEL" }, { col => 1, table => 1, text => "19:15" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "CK_AUTO_EN" }, { col => 1, table => 1, text => 20 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=No CK duty cycle correction " }, { col => 3, table => 1, text => " 1=Correct CK duty cycle " }, { col => 0, table => 1, text => "CK_DELAY_SEL" }, { col => 1, table => 1, text => 21 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Use register value " }, { col => 3, table => 1, text => " 1=Use auto cal value " }, { col => 0, table => 1, text => "CK_DELAY_N" }, { col => 1, table => 1, text => "23:22" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "CK_DELAY_P" }, { col => 1, table => 1, text => "25:24" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2708]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, ], }, { num => 35, text => [ { col => 0, table => 0, text => "DELAY_DATA_SYNC" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay data sync " }, { col => 3, table => 0, text => " 1=delay data sync by 1 yclk " }, { col => 0, table => 0, text => "DELAY_STR_SYNC" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay strobe sync " }, { col => 3, table => 0, text => " 1=delay strobe sync by 1 yclk " }, { col => 0, table => 0, text => "DELAY_CLK_SYNC" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay clk sync " }, { col => 3, table => 0, text => " 1=delay clk sync by 1 yclk " }, { col => 0, table => 0, text => "DELAY_CMD_SYNC" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay cmd sync " }, { col => 3, table => 0, text => " 1=delay cmd sync by 1 yclk " }, { col => 0, table => 0, text => "DELAY_ADR_SYNC" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay adr sync " }, { col => 3, table => 0, text => " 1=delay adr sync by 1 yclk " }, { col => 0, table => 0, text => "MEM_FALL_OUT_DATA" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Data out on YCLK rise " }, { col => 3, table => 0, text => " 1=Data out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "MEM_FALL_OUT_STR" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Strobe out on YCLK rise " }, { col => 3, table => 0, text => " 1=Strobe out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "MEM_FALL_OUT_CLK" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Clk out on YCLK rise " }, { col => 3, table => 0, text => " 1=Clk out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "MEM_FALL_OUT_CMD" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Command out on YCLK rise " }, { col => 3, table => 0, text => " 1=Command out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "MEM_FALL_OUT_ADR" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Address out on YCLK rise " }, { col => 3, table => 0, text => " 1=Address out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "FORCE_EN_RD_STR" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Read strb enabled by MC " }, { col => 3, table => 0, text => " 1=Always enable read strb " }, { col => 0, table => 0, text => "EN_RD_STR_DLY" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=count rising edge " }, { col => 3, table => 0, text => " 1=count falling edge " }, { col => 0, table => 0, text => "DISABLE_CMD" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Drive command " }, { col => 3, table => 0, text => " 1=Disable command " }, { col => 0, table => 0, text => "DISABLE_ADR" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Drive address " }, { col => 3, table => 0, text => " 1=Disable address " }, { col => 0, table => 0, text => "VREFI_EN" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=VREFI disable " }, { col => 3, table => 0, text => " 1=VREFI enable " }, { col => 0, table => 0, text => "VREFI_SEL" }, { col => 1, table => 0, text => "19:15" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "CK_AUTO_EN" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No CK duty cycle correction " }, { col => 3, table => 0, text => " 1=Correct CK duty cycle " }, { col => 0, table => 0, text => "CK_DELAY_SEL" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Use register value " }, { col => 3, table => 0, text => " 1=Use auto cal value " }, { col => 0, table => 0, text => "CK_DELAY_N" }, { col => 1, table => 0, text => "23:22" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "CK_DELAY_P" }, { col => 1, table => 0, text => "25:24" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_RD_DQ_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2710]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "MADJ0" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "MADJ1" }, { col => 1, table => 1, text => "15:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "MADJ2" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "MADJ3" }, { col => 1, table => 1, text => "31:24" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_RD_DQ_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2714]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "MADJ0" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "MADJ1" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "MADJ2" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "MADJ3" }, { col => 1, table => 2, text => "31:24" }, { col => 2, table => 2, text => "0x0" }, ], }, { num => 36, text => [ { col => "heading", table => 0, text => "MC_IO_RD_QS_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2718]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DLY0" }, { col => 1, table => 0, text => "7:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DLY1" }, { col => 1, table => 0, text => "15:8" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DLY2" }, { col => 1, table => 0, text => "23:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DLY3" }, { col => 1, table => 0, text => "31:24" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_RD_QS_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x271C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DLY0" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY1" }, { col => 1, table => 1, text => "15:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY2" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY3" }, { col => 1, table => 1, text => "31:24" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_RD_QS2_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2720]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DLY0" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY1" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY2" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY3" }, { col => 1, table => 2, text => "31:24" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_IO_RD_QS2_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2724]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DLY0" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY1" }, { col => 1, table => 3, text => "15:8" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY2" }, { col => 1, table => 3, text => "23:16" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY3" }, { col => 1, table => 3, text => "31:24" }, { col => 2, table => 3, text => "0x0" }, { col => "heading", table => 4, text => "MC_IO_WR_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2728]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "CK_DLY" }, { col => 1, table => 4, text => "2:0" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "CMD_DLY" }, { col => 1, table => 4, text => "5:3" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "ADR_DLY" }, { col => 1, table => 4, text => "8:6" }, { col => 2, table => 4, text => "0x0" }, ], }, { num => 37, text => [ { col => "heading", table => 0, text => "MC_IO_WR_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x272C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "CK_DLY" }, { col => 1, table => 0, text => "2:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "CMD_DLY" }, { col => 1, table => 0, text => "5:3" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "ADR_DLY" }, { col => 1, table => 0, text => "8:6" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_CK_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2730]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "PTERM" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NTERM" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PDRV" }, { col => 1, table => 1, text => "11:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NDRV" }, { col => 1, table => 1, text => "15:12" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "RECV_DUTY" }, { col => 1, table => 1, text => "17:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DRV_DUTY" }, { col => 1, table => 1, text => "19:18" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PREAMP" }, { col => 1, table => 1, text => "21:20" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SELFTIME" }, { col => 1, table => 1, text => 22 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SLEW" }, { col => 1, table => 1, text => "24:23" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VMODE" }, { col => 1, table => 1, text => 25 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VREF_INT" }, { col => 1, table => 1, text => "27:26" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VREF_INTR" }, { col => 1, table => 1, text => 28 }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_CK_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2734]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "PTERM" }, { col => 1, table => 2, text => "3:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NTERM" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PDRV" }, { col => 1, table => 2, text => "11:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NDRV" }, { col => 1, table => 2, text => "15:12" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "RECV_DUTY" }, { col => 1, table => 2, text => "17:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DRV_DUTY" }, { col => 1, table => 2, text => "19:18" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PREAMP" }, { col => 1, table => 2, text => "21:20" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SELFTIME" }, { col => 1, table => 2, text => 22 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SLEW" }, { col => 1, table => 2, text => "24:23" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "VMODE" }, { col => 1, table => 2, text => 25 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "VREF_INT" }, { col => 1, table => 2, text => "27:26" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "VREF_INTR" }, { col => 1, table => 2, text => 28 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "MC_IO_CMD_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2738]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "PTERM" }, { col => undef, table => undef, text => "3:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "NTERM" }, { col => undef, table => undef, text => "7:4" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "PDRV" }, { col => undef, table => undef, text => "11:8" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "NDRV" }, { col => undef, table => undef, text => "15:12" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "RECV_DUTY" }, { col => undef, table => undef, text => "17:16" }, { col => undef, table => undef, text => "0x0" }, ], }, { num => 38, text => [ { col => undef, table => undef, text => "DRV_DUTY" }, { col => undef, table => undef, text => "19:18" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "PREAMP" }, { col => undef, table => undef, text => "21:20" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "SELFTIME" }, { col => undef, table => undef, text => 22 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "SLEW" }, { col => undef, table => undef, text => "24:23" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "VMODE" }, { col => undef, table => undef, text => 25 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "VREF_INT" }, { col => undef, table => undef, text => "27:26" }, { col => undef, table => undef, text => "0x0" }, { col => "heading", table => 0, text => "MC_IO_CMD_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x273C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "PTERM" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NTERM" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PDRV" }, { col => 1, table => 0, text => "11:8" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NDRV" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "RECV_DUTY" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DRV_DUTY" }, { col => 1, table => 0, text => "19:18" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PREAMP" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SELFTIME" }, { col => 1, table => 0, text => 22 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SLEW" }, { col => 1, table => 0, text => "24:23" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "VMODE" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "VREF_INT" }, { col => 1, table => 0, text => "27:26" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_DQ_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2740]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "PTERM" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NTERM" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PDRV" }, { col => 1, table => 1, text => "11:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NDRV" }, { col => 1, table => 1, text => "15:12" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "RECV_DUTY" }, { col => 1, table => 1, text => "17:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DRV_DUTY" }, { col => 1, table => 1, text => "19:18" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PREAMP" }, { col => 1, table => 1, text => "21:20" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SELFTIME" }, { col => 1, table => 1, text => 22 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SLEW" }, { col => 1, table => 1, text => "24:23" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VMODE" }, { col => 1, table => 1, text => 25 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VREF_INT" }, { col => 1, table => 1, text => "27:26" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_DQ_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2744]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "PTERM" }, { col => 1, table => 2, text => "3:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NTERM" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PDRV" }, { col => 1, table => 2, text => "11:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NDRV" }, { col => 1, table => 2, text => "15:12" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "RECV_DUTY" }, { col => 1, table => 2, text => "17:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DRV_DUTY" }, { col => 1, table => 2, text => "19:18" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PREAMP" }, { col => 1, table => 2, text => "21:20" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SELFTIME" }, { col => 1, table => 2, text => 22 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SLEW" }, { col => 1, table => 2, text => "24:23" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "VMODE" }, { col => 1, table => 2, text => 25 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "VREF_INT" }, { col => 1, table => 2, text => "27:26" }, { col => 2, table => 2, text => "0x0" }, ], }, { num => 39, text => [ { col => "heading", table => 0, text => "MC_IO_QS_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2748]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "PTERM" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NTERM" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PDRV" }, { col => 1, table => 0, text => "11:8" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NDRV" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "RECV_DUTY" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DRV_DUTY" }, { col => 1, table => 0, text => "19:18" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PREAMP" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SELFTIME" }, { col => 1, table => 0, text => 22 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SLEW" }, { col => 1, table => 0, text => "24:23" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "VMODE" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "VREF_INT" }, { col => 1, table => 0, text => "27:26" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_QS_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x274C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "PTERM" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NTERM" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PDRV" }, { col => 1, table => 1, text => "11:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NDRV" }, { col => 1, table => 1, text => "15:12" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "RECV_DUTY" }, { col => 1, table => 1, text => "17:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DRV_DUTY" }, { col => 1, table => 1, text => "19:18" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PREAMP" }, { col => 1, table => 1, text => "21:20" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SELFTIME" }, { col => 1, table => 1, text => 22 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SLEW" }, { col => 1, table => 1, text => "24:23" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VMODE" }, { col => 1, table => 1, text => 25 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VREF_INT" }, { col => 1, table => 1, text => "27:26" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_A_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2750]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "PTERM" }, { col => 1, table => 2, text => "3:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NTERM" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PDRV" }, { col => 1, table => 2, text => "11:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NDRV" }, { col => 1, table => 2, text => "15:12" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "RECV_DUTY" }, { col => 1, table => 2, text => "17:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DRV_DUTY" }, { col => 1, table => 2, text => "19:18" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PREAMP" }, { col => 1, table => 2, text => "21:20" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SELFTIME" }, { col => 1, table => 2, text => 22 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SLEW" }, { col => 1, table => 2, text => "24:23" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "VMODE" }, { col => 1, table => 2, text => 25 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "VREF_INT" }, { col => 1, table => 2, text => "27:26" }, { col => 2, table => 2, text => "0x0" }, ], }, { num => 40, text => [ { col => "heading", table => 0, text => "MC_IO_A_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2754]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "PTERM" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NTERM" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PDRV" }, { col => 1, table => 0, text => "11:8" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NDRV" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "RECV_DUTY" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DRV_DUTY" }, { col => 1, table => 0, text => "19:18" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PREAMP" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SELFTIME" }, { col => 1, table => 0, text => 22 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SLEW" }, { col => 1, table => 0, text => "24:23" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "VMODE" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "VREF_INT" }, { col => 1, table => 0, text => "27:26" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_WR_DQ_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2758]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DLY0" }, { col => 1, table => 1, text => "2:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY1" }, { col => 1, table => 1, text => "5:3" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY2" }, { col => 1, table => 1, text => "8:6" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY3" }, { col => 1, table => 1, text => "11:9" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "MC_IO_WR_DQ_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x275C]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DLY0" }, { col => undef, table => undef, text => "2:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "DLY1" }, { col => undef, table => undef, text => "5:3" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "DLY2" }, { col => undef, table => undef, text => "8:6" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "DLY3" }, { col => undef, table => undef, text => "11:9" }, { col => undef, table => undef, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_WR_QS_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2760]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DLY0" }, { col => 1, table => 2, text => "2:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY1" }, { col => 1, table => 2, text => "5:3" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY2" }, { col => 1, table => 2, text => "8:6" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY3" }, { col => 1, table => 2, text => "11:9" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_IO_WR_QS_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2764]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DLY0" }, { col => 1, table => 3, text => "2:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY1" }, { col => 1, table => 3, text => "5:3" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY2" }, { col => 1, table => 3, text => "8:6" }, { col => 2, table => 3, text => "0x0" }, ], }, { num => 41, text => [ { col => 0, table => 0, text => "DLY3" }, { col => 1, table => 0, text => "11:9" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_RD_STR_NCNTL_B0_D0 - RW - 32 bits - [GpuF0MMReg:0x26E8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "SEL0" }, { col => 1, table => 1, text => "2:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bit0 select" }, { col => 0, table => 1, text => "SEL1" }, { col => 1, table => 1, text => "5:3" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bit1 select" }, { col => 0, table => 1, text => "SEL2" }, { col => 1, table => 1, text => "8:6" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bit2 select" }, { col => 0, table => 1, text => "SEL3" }, { col => 1, table => 1, text => "11:9" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bit3 select" }, { col => 0, table => 1, text => "SEL4" }, { col => 1, table => 1, text => "14:12" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bit4 select" }, { col => 0, table => 1, text => "SEL5" }, { col => 1, table => 1, text => "17:15" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bit5 select" }, { col => 0, table => 1, text => "SEL6" }, { col => 1, table => 1, text => "20:18" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bit6 select" }, { col => 0, table => 1, text => "SEL7" }, { col => 1, table => 1, text => "23:21" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bit7 select" }, { col => 0, table => 1, text => "SELM" }, { col => 1, table => 1, text => "26:24" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Falling Edge Strobe Select For Read Data Byte0", }, { col => "heading", table => 2, text => "MC_IO_RD_STR_NCNTL_B1_D0 - RW - 32 bits - [GpuF0MMReg:0x280C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "SEL0" }, { col => 1, table => 2, text => "2:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bit0 select" }, { col => 0, table => 2, text => "SEL1" }, { col => 1, table => 2, text => "5:3" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bit1 select" }, { col => 0, table => 2, text => "SEL2" }, { col => 1, table => 2, text => "8:6" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bit2 select" }, { col => 0, table => 2, text => "SEL3" }, { col => 1, table => 2, text => "11:9" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bit3 select" }, { col => 0, table => 2, text => "SEL4" }, { col => 1, table => 2, text => "14:12" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bit4 select" }, { col => 0, table => 2, text => "SEL5" }, { col => 1, table => 2, text => "17:15" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bit5 select" }, { col => 0, table => 2, text => "SEL6" }, { col => 1, table => 2, text => "20:18" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bit6 select" }, { col => 0, table => 2, text => "SEL7" }, { col => 1, table => 2, text => "23:21" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bit7 select" }, { col => 0, table => 2, text => "SELM" }, { col => 1, table => 2, text => "26:24" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Falling Edge Strobe Select For Read Data Byte1", }, { col => "heading", table => 3, text => "MC_IO_RD_STR_NCNTL_B2_D0 - RW - 32 bits - [GpuF0MMReg:0x26F8]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "SEL0" }, { col => 1, table => 3, text => "2:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bit0 select" }, { col => 0, table => 3, text => "SEL1" }, { col => 1, table => 3, text => "5:3" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bit1 select" }, { col => 0, table => 3, text => "SEL2" }, { col => 1, table => 3, text => "8:6" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bit2 select" }, { col => 0, table => 3, text => "SEL3" }, { col => 1, table => 3, text => "11:9" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bit3 select" }, { col => 0, table => 3, text => "SEL4" }, { col => 1, table => 3, text => "14:12" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bit4 select" }, { col => 0, table => 3, text => "SEL5" }, { col => 1, table => 3, text => "17:15" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bit5 select" }, { col => 0, table => 3, text => "SEL6" }, { col => 1, table => 3, text => "20:18" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bit6 select" }, { col => 0, table => 3, text => "SEL7" }, { col => 1, table => 3, text => "23:21" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bit7 select" }, { col => 0, table => 3, text => "SELM" }, { col => 1, table => 3, text => "26:24" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Falling Edge Strobe Select For Read Data Byte2", }, { col => undef, table => undef, text => "MC_IO_RD_STR_NCNTL_B3_D0 - RW - 32 bits - [GpuF0MMReg:0x27F8]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "SEL0" }, { col => undef, table => undef, text => "2:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Bit0 select" }, ], }, { num => 42, text => [ { col => 0, table => 0, text => "SEL1" }, { col => 1, table => 0, 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=> 3, table => 2, text => " 0=Ignore cal ctl str " }, { col => 3, table => 2, text => " 1=Use cal ctl str " }, { col => 0, table => 2, text => "LOAD_STR" }, { col => 1, table => 2, text => 13 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PSTR_OFF_V" }, { col => 1, table => 2, text => "19:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NSTR_OFF_V" }, { col => 1, table => 2, text => "23:20" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_SEQ_QS_PAD_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x2780]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "NMOS_PD" }, { col => 1, table => 3, text => "1:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_H" }, { col => 1, table => 3, text => "7:4" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_H" }, { col => 1, table => 3, text => "11:8" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "USE_CAL_STR" }, { col => 1, table => 3, text => 12 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=Ignore cal ctl str " }, { col => 3, table => 3, text => " 1=Use cal ctl str " }, ], }, { num => 45, text => [ { col => 0, table => 0, text => "LOAD_STR" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PSTR_OFF_V" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NSTR_OFF_V" }, { col => 1, table => 0, text => "23:20" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_SEQ_QS_PAD_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x2784]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "NMOS_PD" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PSTR_OFF_H" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NSTR_OFF_H" }, { col => 1, table => 1, text => "11:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "USE_CAL_STR" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Ignore cal ctl str " }, { col => 3, table => 1, text => " 1=Use cal ctl str " }, { col => 0, table => 1, text => "LOAD_STR" }, { col => 1, table => 1, text => 13 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PSTR_OFF_V" }, { col => 1, table => 1, text => "19:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NSTR_OFF_V" }, { col => 1, table => 1, text => "23:20" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_SEQ_A_PAD_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x2788]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "NMOS_PD" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PSTR_OFF_H" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NSTR_OFF_H" }, { col => 1, table => 2, text => "11:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "USE_CAL_STR" }, { col => 1, table => 2, text => 12 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Ignore cal ctl str " }, { col => 3, table => 2, text => " 1=Use cal ctl str " }, { col => 0, table => 2, text => "LOAD_STR" }, { col => 1, table => 2, text => 13 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PSTR_OFF_V" }, { col => 1, table => 2, text => "19:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NSTR_OFF_V" }, { col => 1, table => 2, text => "23:20" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_SEQ_A_PAD_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x278C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "NMOS_PD" }, { col => 1, table => 3, text => "1:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_H" }, { col => 1, table => 3, text => "7:4" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_H" }, { col => 1, table => 3, text => "11:8" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "USE_CAL_STR" }, { col => 1, table => 3, text => 12 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=Ignore cal ctl str " }, { col => 3, table => 3, text => " 1=Use cal ctl str " }, { col => 0, table => 3, text => "LOAD_STR" }, { col => 1, table => 3, text => 13 }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_V" }, { col => 1, table => 3, text => "19:16" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_V" }, { col => 1, table => 3, text => "23:20" }, { col => 2, table => 3, text => "0x0" }, { col => "heading", table => 4, text => "MC_IO_PAD_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x2790]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, ], }, { num => 46, text => [ { col => 0, table => 0, text => "DELAY_DATA_SYNC" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay data sync " }, { col => 3, table => 0, text => " 1=delay data sync by 1 yclk " }, { col => 0, table => 0, text => "DELAY_STR_SYNC" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay strobe sync " }, { col => 3, table => 0, text => " 1=delay strobe sync by 1 yclk " }, { col => 0, table => 0, text => "DELAY_CLK_SYNC" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay clk sync " }, { col => 3, table => 0, text => " 1=delay clk sync by 1 yclk " }, { col => 0, table => 0, text => "DELAY_CMD_SYNC" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay cmd sync " }, { col => 3, table => 0, text => " 1=delay cmd sync by 1 yclk " }, { col => 0, table => 0, text => "DELAY_ADR_SYNC" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay adr sync " }, { col => 3, table => 0, text => " 1=delay adr sync by 1 yclk " }, { col => 0, table => 0, text => "MEM_FALL_OUT_DATA" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Data out on YCLK rise " }, { col => 3, table => 0, text => " 1=Data out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "MEM_FALL_OUT_STR" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Strobe out on YCLK rise " }, { col => 3, table => 0, text => " 1=Strobe out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "MEM_FALL_OUT_CLK" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Clk out on YCLK rise " }, { col => 3, table => 0, text => " 1=Clk out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "MEM_FALL_OUT_CMD" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Command out on YCLK rise " }, { col => 3, table => 0, text => " 1=Command out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "MEM_FALL_OUT_ADR" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Address out on YCLK rise " }, { col => 3, table => 0, text => " 1=Address out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "FORCE_EN_RD_STR" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Read strb enabled by MC " }, { col => 3, table => 0, text => " 1=Always enable read strb " }, { col => 0, table => 0, text => "EN_RD_STR_DLY" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=count rising edge " }, { col => 3, table => 0, text => " 1=count falling edge " }, { col => 0, table => 0, text => "DISABLE_CMD" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Drive command " }, { col => 3, table => 0, text => " 1=Disable command " }, { col => 0, table => 0, text => "DISABLE_ADR" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Drive address " }, { col => 3, table => 0, text => " 1=Disable address " }, { col => 0, table => 0, text => "VREFI_EN" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=VREFI disable " }, { col => 3, table => 0, text => " 1=VREFI enable " }, { col => 0, table => 0, text => "VREFI_SEL" }, { col => 1, table => 0, text => "19:15" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "CK_AUTO_EN" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No CK duty cycle correction " }, { col => 3, table => 0, text => " 1=Correct CK duty cycle " }, { col => 0, table => 0, text => "CK_DELAY_SEL" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Use register value " }, { col => 3, table => 0, text => " 1=Use auto cal value " }, { col => 0, table => 0, text => "CK_DELAY_N" }, { col => 1, table => 0, text => "23:22" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "CK_DELAY_P" }, { col => 1, table => 0, text => "25:24" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_PAD_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x2794]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DELAY_DATA_SYNC" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay data sync " }, { col => 3, table => 1, text => " 1=delay data sync by 1 yclk " }, { col => 0, table => 1, text => "DELAY_STR_SYNC" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay strobe sync " }, { col => 3, table => 1, text => " 1=delay strobe sync by 1 yclk " }, { col => 0, table => 1, text => "DELAY_CLK_SYNC" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay clk sync " }, { col => 3, table => 1, text => " 1=delay clk sync by 1 yclk " }, { col => 0, table => 1, text => "DELAY_CMD_SYNC" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay cmd sync " }, { col => 3, table => 1, text => " 1=delay cmd sync by 1 yclk " }, { col => 0, table => 1, text => "DELAY_ADR_SYNC" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay adr sync " }, { col => 3, table => 1, text => " 1=delay adr sync by 1 yclk " }, { col => 0, table => 1, text => "MEM_FALL_OUT_DATA" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Data out on YCLK rise " }, { col => 3, table => 1, text => " 1=Data out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 1, text => "MEM_FALL_OUT_STR" }, { col => 1, table => 1, text => 6 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Strobe out on YCLK rise " }, { col => 3, table => 1, text => " 1=Strobe out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 1, text => "MEM_FALL_OUT_CLK" }, { col => 1, table => 1, text => 7 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Clk out on YCLK rise " }, { col => 3, table => 1, text => " 1=Clk out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 1, text => "MEM_FALL_OUT_CMD" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Command out on YCLK rise " }, { col => 3, table => 1, text => " 1=Command out on YCLK fall, 1/4 clock delay ", }, ], }, { num => 47, text => [ { col => 0, table => 0, text => "MEM_FALL_OUT_ADR" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Address out on YCLK rise " }, { col => 3, table => 0, text => " 1=Address out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "FORCE_EN_RD_STR" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Read strb enabled by MC " }, { col => 3, table => 0, text => " 1=Always enable read strb " }, { col => 0, table => 0, text => "EN_RD_STR_DLY" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=count rising edge " }, { col => 3, table => 0, text => " 1=count falling edge " }, { col => 0, table => 0, text => "DISABLE_CMD" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Drive command " }, { col => 3, table => 0, text => " 1=Disable command " }, { col => 0, table => 0, text => "DISABLE_ADR" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Drive address " }, { col => 3, table => 0, text => " 1=Disable address " }, { col => 0, table => 0, text => "VREFI_EN" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=VREFI disable " }, { col => 3, table => 0, text => " 1=VREFI enable " }, { col => 0, table => 0, text => "VREFI_SEL" }, { col => 1, table => 0, text => "19:15" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "CK_AUTO_EN" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No CK duty cycle correction " }, { col => 3, table => 0, text => " 1=Correct CK duty cycle " }, { col => 0, table => 0, text => "CK_DELAY_SEL" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Use register value " }, { col => 3, table => 0, text => " 1=Use auto cal value " }, { col => 0, table => 0, text => "CK_DELAY_N" }, { col => 1, table => 0, text => "23:22" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "CK_DELAY_P" }, { col => 1, table => 0, text => "25:24" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_RD_DQ_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x2798]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "MADJ0" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "MADJ1" }, { col => 1, table => 1, text => "15:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "MADJ2" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "MADJ3" }, { col => 1, table => 1, text => "31:24" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_RD_DQ_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x279C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "MADJ0" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "MADJ1" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "MADJ2" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "MADJ3" }, { col => 1, table => 2, text => "31:24" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_IO_RD_QS_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x27A0]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DLY0" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY1" }, { col => 1, table => 3, text => "15:8" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY2" }, { col => 1, table => 3, text => "23:16" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY3" }, { col => 1, table => 3, text => "31:24" }, { col => 2, table => 3, text => "0x0" }, ], }, { num => 48, text => [ { col => "heading", table => 0, text => "MC_IO_RD_QS_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x27A4]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DLY0" }, { col => 1, table => 0, text => "7:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DLY1" }, { col => 1, table => 0, text => "15:8" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DLY2" }, { col => 1, table => 0, text => "23:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DLY3" }, { col => 1, table => 0, text => "31:24" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_RD_QS2_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x27A8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DLY0" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY1" }, { col => 1, table => 1, text => "15:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY2" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY3" }, { col => 1, table => 1, text => "31:24" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_RD_QS2_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x27AC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DLY0" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY1" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY2" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY3" }, { col => 1, table => 2, text => "31:24" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_IO_WR_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x27B0]", }, { col => 0, table => 3, text => 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text => "RECV_DUTY" }, { col => 1, table => 1, text => "17:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DRV_DUTY" }, { col => 1, table => 1, text => "19:18" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PREAMP" }, { col => 1, table => 1, text => "21:20" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SELFTIME" }, { col => 1, table => 1, text => 22 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SLEW" }, { col => 1, table => 1, text => "24:23" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VMODE" }, { col => 1, table => 1, text => 25 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VREF_INT" }, { col => 1, table => 1, text => "27:26" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_A_PAD_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x27DC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "PTERM" }, { col => 1, table => 2, text => "3:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NTERM" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PDRV" }, { col => 1, table => 2, text => "11:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NDRV" }, { col => 1, table => 2, text => "15:12" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "RECV_DUTY" }, { col => 1, table => 2, text => "17:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DRV_DUTY" }, { col => 1, table => 2, text => "19:18" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PREAMP" }, { col => 1, table => 2, text => "21:20" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SELFTIME" }, { col => 1, table => 2, text => 22 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SLEW" }, { col => 1, table => 2, text => "24:23" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "VMODE" }, { col => 1, table => 2, text => 25 }, { col => 2, table => 2, text => "0x0" }, ], }, { num => 52, text => [ { col => 0, table => 0, text => "VREF_INT" }, { col => 1, table => 0, text => "27:26" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_WR_DQ_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x27E0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DLY0" }, { col => 1, table => 1, text => "2:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY1" }, { col => 1, table => 1, text => "5:3" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY2" }, { col => 1, table => 1, text => "8:6" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY3" }, { col => 1, table => 1, text => "11:9" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_WR_DQ_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x27E4]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DLY0" }, { col => 1, table => 2, text => "2:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY1" }, { col => 1, table => 2, text => "5:3" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY2" }, { col => 1, table => 2, text => "8:6" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY3" }, { col => 1, table => 2, text => "11:9" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_IO_WR_QS_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x27E8]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DLY0" }, { col => 1, table => 3, text => "2:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY1" }, { col => 1, table => 3, text => "5:3" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY2" }, { col => 1, table => 3, text => "8:6" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY3" }, { col => 1, table => 3, text => "11:9" }, { col => 2, table => 3, text => "0x0" }, { col => "heading", table => 4, text => "MC_IO_WR_QS_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x27EC]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "DLY0" }, { col => 1, table => 4, text => "2:0" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "DLY1" }, { col => 1, table => 4, text => "5:3" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "DLY2" }, { col => 1, table => 4, text => "8:6" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "DLY3" }, { col => 1, table => 4, text => "11:9" }, { col => 2, table => 4, text => "0x0" }, { col => "heading", table => 5, text => "MC_IO_RD_STR_NCNTL_B0_D1 - RW - 32 bits - [GpuF0MMReg:0x2820]", }, { col => 0, table => 5, text => "Field Name" }, { col => 1, table => 5, text => "Bits" }, { col => 2, table => 5, text => "Default" }, { col => 3, table => 5, text => "Description" }, { col => 0, table => 5, text => "SEL0" }, { col => 1, table => 5, text => "2:0" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "SEL1" }, { col => 1, table => 5, text => "5:3" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "SEL2" }, { col => 1, table => 5, text => "8:6" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "SEL3" }, { col => 1, table => 5, text => "11:9" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "SEL4" }, { col => 1, table => 5, text => "14:12" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "SEL5" }, { col => 1, table => 5, text => "17:15" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "SEL6" }, { col => 1, table => 5, text => "20:18" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "SEL7" }, { col => 1, table => 5, text => "23:21" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "SELM" }, { col => 1, table => 5, text => "26:24" }, { col => 2, table => 5, text => "0x0" }, { col => undef, table => undef, text => "MC_IO_RD_STR_NCNTL_B1_D1 - RW - 32 bits - [GpuF0MMReg:0x2828]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, ], }, { num => 53, text => [ { col => 0, table => 0, text => "SEL0" }, { col => 1, table => 0, text => "2:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL1" }, { col => 1, table => 0, text => "5:3" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL2" }, { col => 1, table => 0, text => "8:6" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL3" }, { col => 1, table => 0, text => "11:9" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL4" }, { col => 1, table => 0, text => "14:12" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL5" }, { col => 1, table => 0, text => "17:15" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL6" }, { col => 1, table => 0, text => "20:18" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL7" }, { col => 1, table => 0, text => "23:21" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SELM" }, { col => 1, table => 0, text => "26:24" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_RD_STR_NCNTL_B2_D1 - RW - 32 bits - [GpuF0MMReg:0x2830]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "SEL0" }, { col => 1, table => 1, text => "2:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL1" }, { col => 1, table => 1, text => "5:3" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL2" }, { col => 1, table => 1, text => "8:6" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL3" }, { col => 1, table => 1, text => "11:9" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL4" }, { col => 1, table => 1, text => "14:12" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL5" }, { col => 1, table => 1, text => "17:15" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL6" }, { col => 1, table => 1, text => "20:18" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL7" }, { col => 1, table => 1, text => "23:21" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SELM" }, { col => 1, table => 1, text => "26:24" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_RD_STR_NCNTL_B3_D1 - RW - 32 bits - [GpuF0MMReg:0x2838]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "SEL0" }, { col => 1, table => 2, text => "2:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SEL1" }, { col => 1, table => 2, text => "5:3" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SEL2" }, { col => 1, table => 2, text => "8:6" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SEL3" }, { col => 1, table => 2, text => "11:9" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SEL4" }, { col => 1, table => 2, text => "14:12" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SEL5" }, { col => 1, table => 2, text => "17:15" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SEL6" }, { col => 1, table => 2, text => "20:18" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SEL7" }, { col => 1, table => 2, text => "23:21" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SELM" }, { col => 1, table => 2, text => "26:24" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_IO_RD_STR_NCNTL_B4_D1 - RW - 32 bits - [GpuF0MMReg:0x2840]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "SEL0" }, { col => 1, table => 3, text => "2:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SEL1" }, { col => 1, table => 3, text => "5:3" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SEL2" }, { col => 1, table => 3, text => "8:6" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SEL3" }, { col => 1, table => 3, text => "11:9" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SEL4" }, { col => 1, table => 3, text => "14:12" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SEL5" }, { col => 1, table => 3, text => "17:15" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SEL6" }, { col => 1, table => 3, text => "20:18" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SEL7" }, { col => 1, table => 3, text => "23:21" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SELM" }, { col => 1, table => 3, text => "26:24" }, { col => 2, table => 3, text => "0x0" }, { col => "heading", table => 4, text => "MC_IO_RD_STR_NCNTL_B5_D1 - RW - 32 bits - [GpuF0MMReg:0x2848]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "SEL0" }, { col => 1, table => 4, text => "2:0" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "SEL1" }, { col => 1, table => 4, text => "5:3" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "SEL2" }, { col => 1, table => 4, text => "8:6" }, { col => 2, table => 4, text => "0x0" }, ], }, { num => 54, text => [ { col => undef, table => undef, text => "SEL3" }, { col => undef, table => undef, text => "11:9" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "SEL4" }, { col => undef, table => undef, text => "14:12" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "SEL5" }, { col => undef, table => undef, text => "17:15" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "SEL6" }, { col => undef, table => undef, text => "20:18" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "SEL7" }, { col => undef, table => undef, text => "23:21" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "SELM" }, { col => undef, table => undef, text => "26:24" }, { col => undef, table => undef, text => "0x0" }, { col => "heading", table => 0, text => "MC_IO_RD_STR_NCNTL_B6_D1 - RW - 32 bits - [GpuF0MMReg:0x2850]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "SEL0" }, { col => 1, table => 0, text => "2:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL1" }, { col => 1, table => 0, text => "5:3" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL2" }, { col => 1, table => 0, text => "8:6" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL3" }, { col => 1, table => 0, text => "11:9" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL4" }, { col => 1, table => 0, text => "14:12" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL5" }, { col => 1, table => 0, text => "17:15" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL6" }, { col => 1, table => 0, text => "20:18" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL7" }, { col => 1, table => 0, text => "23:21" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SELM" }, { col => 1, table => 0, text => "26:24" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_RD_STR_NCNTL_B7_D1 - RW - 32 bits - [GpuF0MMReg:0x2858]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "SEL0" }, { col => 1, table => 1, text => "2:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL1" }, { col => 1, table => 1, text => "5:3" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL2" }, { col => 1, table => 1, text => "8:6" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL3" }, { col => 1, table => 1, text => "11:9" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL4" }, { col => 1, table => 1, text => "14:12" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL5" }, { col => 1, table => 1, text => "17:15" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL6" }, { col => 1, table => 1, text => "20:18" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL7" }, { col => 1, table => 1, text => "23:21" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SELM" }, { col => 1, table => 1, text => "26:24" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_SEQ_GENERAL_CONFIG - RW - 32 bits - [GpuF0MMReg:0x26D8]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "MODE_32BIT" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0=64-bit channel mode " }, { col => 3, table => 2, text => " 1=32-bit channel mode " }, { col => 0, table => 2, text => "DUAL_IO" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Single IO configuration " }, { col => 3, table => 2, text => " 1=Dual IO configuration " }, { col => 0, table => 2, text => "MODE_16BIT" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => " 1=16-bit channel mode " }, { col => undef, table => undef, text => "General SEQ configuration" }, { col => "heading", table => 3, text => "MC_SEQ_RS_CNTL - RW - 32 bits - [GpuF0MMReg:0x26DC]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "RRDREQ_LCL_CREDIT" }, { col => 1, table => 3, text => "3:0" }, { col => 2, table => 3, text => "0x4" }, { col => 0, table => 3, text => "XBF_HWM" }, { col => 1, table => 3, text => "9:4" }, { col => 2, table => 3, text => "0x12" }, { col => 3, table => 3, text => "High water mark for mclk to sclk async FIFO, for 64bit BO4, ", }, { col => 3, table => 3, text => "the water mark should be increased" }, { col => 0, table => 3, text => "DAT_INV" }, { col => 1, table => 3, text => 12 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=Disable read data inversion " }, { col => 3, table => 3, text => " 1=Enable read data inversion " }, { col => 0, table => 3, text => "MSK_DFI" }, { col => 1, table => 3, text => 13 }, { col => 2, table => 3, text => "0x1" }, { col => 3, table => 3, text => " 0=Inverse mask active low " }, { col => 3, table => 3, text => " 1=Inverse mask active high " }, ], }, { num => 55, text => [ { col => undef, table => undef, text => "RRDREQ_RETURN_PEND" }, { col => undef, table => undef, text => "17:16" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=Return the read data to RS whenever the data is ready ", }, { col => undef, table => undef, text => " 1=Return the read data to RS after all the data for that ", }, { col => undef, table => undef, text => "burst has been received " }, { col => undef, table => undef, text => " 2=Return the read data to RS when the data is ready and ", }, { col => undef, table => undef, text => "the last read for that burst has been sent out to the memory ", }, { col => undef, table => undef, text => " 3=Reserved " }, { col => undef, table => undef, text => "RRDREQ_RS_CREDIT" }, { col => undef, table => undef, text => "23:20" }, { col => undef, table => undef, text => "0x8" }, { col => undef, table => undef, text => " " }, { col => undef, table => undef, text => "SEQ to RS control register " }, { col => "heading", table => 0, text => "MC_SEQ_STATUS_M - RW - 32 bits - [GpuF0MMReg:0x26C8]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "PWRUP_COMPL_D0 (R)" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=CHAN_D0 SDRAM init in progress " }, { col => 3, table => 0, text => " 1=CHAN_D0 SDRAM ready " }, { col => 0, table => 0, text => "PWRUP_COMPL_D1 (R)" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=CHAN_D1 SDRAM init in progress " }, { col => 3, table => 0, text => " 1=CHAN_D1 SDRAM ready " }, { col => 0, table => 0, text => "CMD_RDY_D0 (R)" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=CHAN_D0 Command register busy " }, { col => 3, table => 0, text => " 1=CHAN_D0 Command register ready " }, { col => 0, table => 0, text => "CMD_RDY_D1 (R)" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=CHAN_D1 Command register busy " }, { col => 3, table => 0, text => " 1=CHAN_D1 Command register ready " }, { col => 0, table => 0, text => "SLF_D0 (R)" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=CHAN_D0 Not in Self Refresh mode " }, { col => 3, table => 0, text => " 1=CHAN_D0 In Self Refresh mode " }, { col => 0, table => 0, text => "SLF_D1 (R)" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=CHAN_D1 Not in Self Refresh mode " }, { col => 3, table => 0, text => " 1=CHAN_D1 In Self Refresh mode " }, { col => 0, table => 0, text => "SEQ00_ARB_CMD_FIFO_EMPTY (R)" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ00 arb interface cmd fifo not empty ", }, { col => 3, table => 0, text => " 1=SEQ00 arb interface cmd fifo empty ", }, { col => 0, table => 0, text => "SEQ01_ARB_CMD_FIFO_EMPTY (R)" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ01 arb interface cmd fifo not empty ", }, { col => 3, table => 0, text => " 1=SEQ01 arb interface cmd fifo empty ", }, { col => 0, table => 0, text => "SEQ10_ARB_CMD_FIFO_EMPTY (R)" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ10 arb interface cmd fifo not empty ", }, { col => 3, table => 0, text => " 1=SEQ10 arb interface cmd fifo empty ", }, { col => 0, table => 0, text => "SEQ11_ARB_CMD_FIFO_EMPTY (R)" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ11 arb interface cmd fifo not empty ", }, { col => 3, table => 0, text => " 1=SEQ11 arb interface cmd fifo empty ", }, { col => 0, table => 0, text => "SEQ00_RS_DATA_FIFO_FULL (R)" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ00 rs interface data fifo not full ", }, { col => 3, table => 0, text => " 1=SEQ00 rs interface data fifo full " }, { col => 0, table => 0, text => "SEQ01_RS_DATA_FIFO_FULL (R)" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ01 rs interface data fifo not full ", }, { col => 3, table => 0, text => " 1=SEQ01 rs interface data fifo full " }, { col => 0, table => 0, text => "SEQ10_RS_DATA_FIFO_FULL (R)" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ10 rs interface data fifo not full ", }, { col => 3, table => 0, text => " 1=SEQ10 rs interface data fifo full " }, { col => 0, table => 0, text => "SEQ11_RS_DATA_FIFO_FULL (R)" }, { col => 1, table => 0, text => 15 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ11 rs interface data fifo not full ", }, { col => 3, table => 0, text => " 1=SEQ11 rs interface data fifo full " }, { col => "heading", table => 1, text => "MC_SEQ_STATUS_S - RW - 32 bits - [GpuF0MMReg:0x288C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "SEQ00_ARB_DATA_FIFO_FULL (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=SEQ00 arb interface data fifo not full ", }, { col => 3, table => 1, text => " 1=SEQ00 arb interface data fifo full ", }, { col => 0, table => 1, text => "SEQ01_ARB_DATA_FIFO_FULL (R)" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=SEQ01 arb interface data fifo not full ", }, { col => 3, table => 1, text => " 1=SEQ01 arb interface data fifo full ", }, { col => 0, table => 1, text => "SEQ10_ARB_DATA_FIFO_FULL (R)" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=SEQ10 arb interface data fifo not full ", }, { col => 3, table => 1, text => " 1=SEQ10 arb interface data fifo full ", }, { col => 0, table => 1, text => "SEQ11_ARB_DATA_FIFO_FULL (R)" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=SEQ11 arb interface data fifo not full ", }, { col => 3, table => 1, text => " 1=SEQ11 arb interface data fifo full ", }, { col => 0, table => 1, text => "SEQ00_ARB_CMD_FIFO_FULL (R)" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=SEQ00 arb interface cmd fifo not full ", }, { col => 3, table => 1, text => " 1=SEQ00 arb interface cmd fifo full " }, { col => 0, table => 1, text => "SEQ01_ARB_CMD_FIFO_FULL (R)" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=SEQ01 arb interface cmd fifo not full ", }, { col => 3, table => 1, text => " 1=SEQ01 arb interface cmd fifo full " }, { col => 0, table => 1, text => "SEQ10_ARB_CMD_FIFO_FULL (R)" }, { col => 1, table => 1, text => 6 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=SEQ10 arb interface cmd fifo not full ", }, { col => 3, table => 1, text => " 1=SEQ10 arb interface cmd fifo full " }, ], }, { num => 56, text => [ { col => 0, table => 0, text => "SEQ11_ARB_CMD_FIFO_FULL (R)" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ11 arb interface cmd fifo not full ", }, { col => 3, table => 0, text => " 1=SEQ11 arb interface cmd fifo full " }, { col => 0, table => 0, text => "SEQ00_RS_DATA_FIFO_EMPTY (R)" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ00 rs interface data fifo not EMPTY ", }, { col => 3, table => 0, text => " 1=SEQ00 rs interface data fifo EMPTY ", }, { col => 0, table => 0, text => "SEQ01_RS_DATA_FIFO_EMPTY (R)" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ01 rs interface data fifo not EMPTY ", }, { col => 3, table => 0, text => " 1=SEQ01 rs interface data fifo EMPTY ", }, { col => 0, table => 0, text => "SEQ10_RS_DATA_FIFO_EMPTY (R)" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ10 rs interface data fifo not EMPTY ", }, { col => 3, table => 0, text => " 1=SEQ10 rs interface data fifo EMPTY ", }, { col => 0, table => 0, text => "SEQ11_RS_DATA_FIFO_EMPTY (R)" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ11 rs interface data fifo not EMPTY ", }, { col => 3, table => 0, text => " 1=SEQ11 rs interface data fifo EMPTY ", }, { col => "heading", table => 1, text => "MC_NPL_STATUS - RW - 32 bits - [GpuF0MMReg:0x2888]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D0_I0_PDELAY (R)" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D0_I0_NDELAY (R)" }, { col => 1, table => 1, text => "3:2" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D0_I0_PEARLY (R)" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D0_I0_NEARLY (R)" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D0_I1_PDELAY (R)" }, { col => 1, table => 1, text => "7:6" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D0_I1_NDELAY (R)" }, { col => 1, table => 1, text => "9:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D0_I1_PEARLY (R)" }, { col => 1, table => 1, text => 10 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D0_I1_NEARLY (R)" }, { col => 1, table => 1, text => 11 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D1_I0_PDELAY (R)" }, { col => 1, table => 1, text => "13:12" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D1_I0_NDELAY (R)" }, { col => 1, table => 1, text => "15:14" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D1_I0_PEARLY (R)" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D1_I0_NEARLY (R)" }, { col => 1, table => 1, text => 17 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D1_I1_PDELAY (R)" }, { col => 1, table => 1, text => "19:18" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D1_I1_NDELAY (R)" }, { col => 1, table => 1, text => "21:20" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D1_I1_PEARLY (R)" }, { col => 1, table => 1, text => 22 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D1_I1_NEARLY (R)" }, { col => 1, table => 1, text => 23 }, { col => 2, table => 1, text => "0x0" }, ], }, { num => 57, text => [ { col => undef, table => undef, text => "2.2" }, { col => undef, table => undef, text => "Bus Interface Registers" }, { col => "heading", table => 0, text => "MM_INDEX - RW - 32 bits - [GpuF0MMReg,GpuIOReg:0x0]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "MM_OFFSET" }, { col => 1, table => 0, text => "30:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This field specifies the offset (in MM space) of the register ", }, { col => 3, table => 0, text => "or the offset in FB memory to be accessed. ", }, { col => 3, table => 0, text => "All accesses must be dword aligned, therefore, ", }, { col => 3, table => 0, text => "bits 1:0 are tied to zero." }, { col => 3, table => 0, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => 0, table => 0, text => "MM_APER" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit specifies whether the address offset is for Register ", }, { col => 3, table => 0, text => "aperture or FB aperture (Linear Aperture).", }, { col => 3, table => 0, text => " 0=Register Aperture " }, { col => undef, table => undef, text => " 1=Linear Aperture 0 " }, { col => undef, table => undef, text => "General Memory Access. The MM_INDEX and MM_DATA pair of registers are used to indirectly accessed ", }, { col => undef, table => undef, text => "all other memory mapped registers in the lower 64KB space and the Frame buffer.", }, { col => "heading", table => 1, text => "MM_DATA - RW - 32 bits - [GpuF0MMReg,GpuIOReg:0x4]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "MM_DATA" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "This field contains the data to be written to or the data read ", }, { col => undef, table => undef, text => "from the address specified in MM_INDEX.", }, { col => undef, table => undef, text => "General Memory Access. The MM_INDEX and MM_DATA pair of registers are used to indirectly access ", }, { col => undef, table => undef, text => "all other BIF memory mapped registers and the frame buffer.", }, { col => "heading", table => 2, text => "BUS_CNTL - RW - 32 bits - [GpuF0MMReg:0x5420]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "BIOS_ROM_WRT_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Unused" }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "BIOS_ROM_DIS" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Unused" }, { col => 3, table => 2, text => " 0=Enable " }, { col => 3, table => 2, text => " 1=Disable " }, { col => 0, table => 2, text => "PMI_IO_DIS" }, { col => 1, table => 2, text => 2 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "The PMI_STATUS_CNTL.POWER_STATE is used to ", }, { col => 3, table => 2, text => "program the power state. If the power ", }, { col => 3, table => 2, text => "state is D1-D3, then IO access is disabled. If this bit is set ", }, { col => 3, table => 2, text => "to 1, it will enable IO access.", }, { col => 3, table => 2, text => " 0=Normal " }, { col => 3, table => 2, text => " 1=Disable " }, { col => 0, table => 2, text => "PMI_MEM_DIS" }, { col => 1, table => 2, text => 3 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "The PMI_STATUS_CNTL.POWER_STATE is used to ", }, { col => 3, table => 2, text => "program the power state. If the power ", }, { col => 3, table => 2, text => "state is D1-D3, then MEM access is disabled. If this bit is ", }, { col => 3, table => 2, text => "set to 1, it will enable MEM access.", }, { col => 3, table => 2, text => " 0=Normal " }, { col => 3, table => 2, text => " 1=Disable " }, ], }, { num => 58, text => [ { col => 0, table => 0, text => "PMI_BM_DIS" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "The PMI_STATUS_CNTL.POWER_STATE is used to ", }, { col => 3, table => 0, text => "program the power state. If the power ", }, { col => 3, table => 0, text => "state is D1-D3, then bus mastering is disabled. If this bit is ", }, { col => 3, table => 0, text => "set to 1, it will enable bus mastering.", }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Disable " }, { col => 0, table => 0, text => "PMI_INT_DIS" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "The PMI_STATUS_CNTL.POWER_STATE is used to ", }, { col => 3, table => 0, text => "program the power state. If the power ", }, { col => 3, table => 0, text => "state is D1-D3, then INTx messages are disabled. If this bit ", }, { col => 3, table => 0, text => "is set to 1, it will enable sending INTx ", }, { col => 3, table => 0, text => "messages." }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Disable " }, { col => 0, table => 0, text => "VGA_REG_COHERENCY_DIS" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Disable VGA register coherency." }, { col => 3, table => 0, text => " 0=Enable " }, { col => 3, table => 0, text => " 1=Disable " }, { col => 0, table => 0, text => "VGA_MEM_COHERENCY_DIS" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Disable VGA memory coherency." }, { col => 3, table => 0, text => " 0=Enable " }, { col => 3, table => 0, text => " 1=Disable " }, { col => 0, table => 0, text => "BIF_ERR_RTR_BKPRESSURE_EN" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable Wrapper backpressure RTR to Gijoe3 when a ", }, { col => 3, table => 0, text => "previous error is pending. When Gijoe3 ", }, { col => 3, table => 0, text => "signals error is done, Wrapper will assert RTR to accept the ", }, { col => 3, table => 0, text => "next request" }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "VGA_COHE_SPEC_TIMER_DIS" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Enable " }, { col => 3, table => 0, text => " 1=Disable " }, { col => 0, table => 0, text => "ALLOW_TC_TO_PCIE" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Allow the traffic class bit from clients to propagate to PCIE ", }, { col => 3, table => 0, text => "core. If not, it will be tied to 0" }, { col => 3, table => 0, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "PCI Express Bus Control Register", }, { col => "heading", table => 1, text => "CONFIG_CNTL - RW - 32 bits - [GpuF0MMReg:0x5424]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CFG_VGA_RAM_EN (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VGA RAM enable" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "VGA_DIS" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VGA Disable. Unused." }, { col => 0, table => 1, text => "GENMO_MONO_ADDRESS_B (R)" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Monochrome emulation or Colour emulation", }, { col => 3, table => 1, text => " 0=Monochrome emulation, regs at 0x3Bx ", }, { col => 3, table => 1, text => " 1=Color/Graphic emulation, regs at 0x3Dx ", }, { col => 0, table => 1, text => "GRPH_ADRSEL (R)" }, { col => 1, table => 1, text => "4:3" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Graphics address and aperture size select", }, { col => 3, table => 1, text => " 0=A0000-128K " }, { col => 3, table => 1, text => " 1=A0000-64K " }, { col => 3, table => 1, text => " 2=B0000-32K " }, { col => undef, table => undef, text => " 3=B8000-32K " }, { col => undef, table => undef, text => "Configuration Control Register" }, { col => "heading", table => 2, text => "CONFIG_MEMSIZE - RW - 32 bits - [GpuF0MMReg:0x5428]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, ], }, { num => 59, text => [ { col => 0, table => 0, text => "CONFIG_MEMSIZE" }, { col => 1, table => 0, text => "31:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Configuration memory size" }, { col => undef, table => undef, text => "NOTE: Bits 0:19 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Scratch regsiter for BIOS to inform driver memory size", }, { col => "heading", table => 1, text => "CONFIG_F0_BASE - R - 32 bits - [GpuF0MMReg:0x542C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "F0_BASE" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "F0 Base Address" }, { col => undef, table => undef, text => "NOTE: Bits 0:24 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Configuration F0 Base Register" }, { col => "heading", table => 2, text => "CONFIG_APER_SIZE - R - 32 bits - [GpuF0MMReg:0x5430]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "APER_SIZE" }, { col => 1, table => 2, text => "31:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Strap-loadable register based on strap MEM_AP_SIZE", }, { col => undef, table => undef, text => "NOTE: Bits 0:23 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Function 0 Configuration Memory Aperture Size", }, { col => "heading", table => 3, text => "CONFIG_REG_APER_SIZE - R - 32 bits - [GpuF0MMReg:0x5434]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "REG_APER_SIZE" }, { col => 1, table => 3, text => "19:0" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Strap-loadable register based on strap REG_AP_SIZE", }, { col => undef, table => undef, text => "Function 0 Configuration Register Aperture Size", }, ], }, { num => 60, text => [ { col => undef, table => undef, text => "2.3" }, { col => undef, table => undef, text => "PCI-E Registers" }, { col => "heading", table => 0, text => "PCIE_INDEX - RW - 32 bits - [GpuF0MMReg,GpuIOReg:0x30]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "PCIE_INDEX" }, { col => 1, table => 0, text => "7:0" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "index of bifdec" }, { col => undef, table => undef, text => "Index register for the PCI Express common indirect registers", }, { col => "heading", table => 1, text => "PCIE_DATA - RW - 32 bits - [GpuF0MMReg,GpuIOReg:0x34]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "PCIE_DATA" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "data of bifdec" }, { col => undef, table => undef, text => "Data register for the PCI Express common indirect registers", }, { col => "heading", table => 2, text => "PCIE_RX_NUM_NACK - R - 32 bits - PCIEIND:0xE", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "RX_NUM_NACK" }, { col => 1, table => 2, text => "31:0" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Total number of nacks received" }, { col => undef, table => undef, text => "Num nacks received" }, { col => "heading", table => 3, text => "PCIE_RX_NUM_NACK_GENERATED - R - 32 bits - PCIEIND:0xF", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "RX_NUM_NACK_GENERATED" }, { col => 1, table => 3, text => "31:0" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Total number of nacks generated" }, { col => undef, table => undef, text => "Num nacks generated" }, { col => "heading", table => 4, text => "PCIE_CI_CNTL - RW - 32 bits - PCIEIND:0x20", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "CI_BE_SPLIT_MODE" }, { col => 1, table => 4, text => "1:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => " 0=Normal byte splitting rules for PCI-Express 1.0A ", }, { col => 3, table => 4, text => " 1=Force a split on QW boundary with maximum packet ", }, { col => 3, table => 4, text => "length = 2 " }, { col => 3, table => 4, text => " 2=Bypass mode that forces full byte enables ", }, { col => 0, table => 4, text => "CI_SLAVE_SPLIT_MODE" }, { col => 1, table => 4, text => 2 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Completions split on Channels" }, { col => 3, table => 4, text => " 0=RC - Full completions from Channel A or B ", }, { col => 3, table => 4, text => " 1=RC - Completions split on Channel A and B evenly ", }, { col => 0, table => 4, text => "CI_SLAVE_GEN_USR_DIS" }, { col => 1, table => 4, text => 3 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Sends USR for invalid addresses" }, { col => 3, table => 4, text => " 0=Sends USR for invalid addresses " }, { col => 3, table => 4, text => " 1=Disables slave from sending USR, and instead ", }, { col => 3, table => 4, text => "sends a successful CMPLT_D with dummy data. ", }, { col => 0, table => 4, text => "CI_MST_CMPL_DUMMY_DATA" }, { col => 1, table => 4, text => 4 }, { col => 2, table => 4, text => "0x1" }, { col => 3, table => 4, text => "0xDEADBEEF or 0xFFFFFFFF" }, { col => 3, table => 4, text => " 0=0xDEADBEEF " }, { col => 3, table => 4, text => " 1=0xFFFFFFFF " }, { col => 0, table => 4, text => "CI_MST_TAG_MODE" }, { col => 1, table => 4, text => 5 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "incremental tag or first available tag" }, { col => 3, table => 4, text => " 0=incremental tag " }, { col => 3, table => 4, text => " 1=first available tag " }, ], }, { num => 61, text => [ { col => 0, table => 0, text => "CI_SLV_RC_RD_REQ_SIZE" }, { col => 1, table => 0, text => "7:6" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Slave read requests supported size to client.", }, { col => 3, table => 0, text => " 0=32/64 byte requests supported " }, { col => 3, table => 0, text => " 1=64 byte requests only " }, { col => 3, table => 0, text => " 2=16/32/64 " }, { col => 0, table => 0, text => "CI_SLV_ORDERING_DIS" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Disable slave ordering logic" }, { col => 3, table => 0, text => " 0=Enable slave ordering logic " }, { col => 3, table => 0, text => " 1=Disable slave ordering logic " }, { col => 0, table => 0, text => "CI_RC_ORDERING_DIS" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Disable RC ordering logic" }, { col => 3, table => 0, text => " 0=Enable RC ordering logic " }, { col => 3, table => 0, text => " 1=Disable RC ordering logic " }, { col => 0, table => 0, text => "CI_SLV_CPL_ALLOC_DIS" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Slave CPL buffer is sub-divided or not" }, { col => 3, table => 0, text => " 0=Slave CPL buffer is sub-divided between ports based ", }, { col => 3, table => 0, text => "on number of lanes active " }, { col => 3, table => 0, text => " 1=Slave CPL buffer is not sub-divided ", }, { col => 0, table => 0, text => "CI_SLV_CPL_ALLOC_MODE (R)" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0Slave Cpl buffer method for sub-division. 0 - dynamic, 1 - ", }, { col => undef, table => undef, text => "register limits CI_SLV_CPL_STATIC_ALLOC_LIMIT_(N)S", }, { col => undef, table => undef, text => "chip interface control register" }, { col => "heading", table => 1, text => "PCIE_LC_STATE6 - R - 32 bits - PCIEIND:0x22", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "LC_PREV_STATE24" }, { col => 1, table => 1, text => "5:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "24th previous state" }, { col => 0, table => 1, text => "LC_PREV_STATE25" }, { col => 1, table => 1, text => "13:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "25th previous state" }, { col => 0, table => 1, text => "LC_PREV_STATE26" }, { col => 1, table => 1, text => "21:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "26th previous state" }, { col => 0, table => 1, text => "LC_PREV_STATE27" }, { col => 1, table => 1, text => "29:24" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "27th previous state" }, { col => undef, table => undef, text => "Link Control State Registers" }, { col => "heading", table => 2, text => "PCIE_LC_STATE7 - R - 32 bits - PCIEIND:0x23", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "LC_PREV_STATE28" }, { col => 1, table => 2, text => "5:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "28th previous state" }, { col => 0, table => 2, text => "LC_PREV_STATE29" }, { col => 1, table => 2, text => "13:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "29th previous state" }, { col => 0, table => 2, text => "LC_PREV_STATE30" }, { col => 1, table => 2, text => "21:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "30th previous state" }, { col => 0, table => 2, text => "LC_PREV_STATE31" }, { col => 1, table => 2, text => "29:24" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "31st previous state" }, { col => undef, table => undef, text => "Link Control State Registers" }, { col => "heading", table => 3, text => "PCIE_LC_STATE8 - R - 32 bits - PCIEIND:0x24", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "LC_PREV_STATE32" }, { col => 1, table => 3, text => "5:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "32nd previous state" }, { col => 0, table => 3, text => "LC_PREV_STATE33" }, { col => 1, table => 3, text => "13:8" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "33rd previous state" }, { col => 0, table => 3, text => "LC_PREV_STATE34" }, { col => 1, table => 3, text => "21:16" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "34th previous state" }, { col => 0, table => 3, text => "LC_PREV_STATE35" }, { col => 1, table => 3, text => "29:24" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "35th previous state" }, { col => undef, table => undef, text => "Link Control State Registers" }, { col => undef, table => undef, text => "PCIE_LC_STATE9 - R - 32 bits - PCIEIND:0x25", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, ], }, { num => 62, text => [ { col => 0, table => 0, text => "LC_PREV_STATE36" }, { col => 1, table => 0, text => "5:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "36th previous state" }, { col => 0, table => 0, text => "LC_PREV_STATE37" }, { col => 1, table => 0, text => "13:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "37th previous state" }, { col => 0, table => 0, text => "LC_PREV_STATE38" }, { col => 1, table => 0, text => "21:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "38th previous state" }, { col => 0, table => 0, text => "LC_PREV_STATE39" }, { col => 1, table => 0, text => "29:24" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "39th previous state" }, { col => undef, table => undef, text => "Link Control State Registers" }, { col => "heading", table => 1, text => "PCIE_LC_STATE10 - R - 32 bits - PCIEIND:0x26", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "LC_PREV_STATE40" }, { col => 1, table => 1, text => "5:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "40th previous state" }, { col => 0, table => 1, text => "LC_PREV_STATE41" }, { col => 1, table => 1, text => "13:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "41st previous state" }, { col => 0, table => 1, text => "LC_PREV_STATE42" }, { col => 1, table => 1, text => "21:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "42nd previous state" }, { col => 0, table => 1, text => "LC_PREV_STATE43" }, { col => 1, table => 1, text => "29:24" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "43rd previous state" }, { col => undef, table => undef, text => "Link Control State Registers" }, { col => "heading", table => 2, text => "PCIE_LC_STATE11 - R - 32 bits - PCIEIND:0x27", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "LC_PREV_STATE44" }, { col => 1, table => 2, text => "5:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "44th previous state" }, { col => 0, table => 2, text => "LC_PREV_STATE45" }, { col => 1, table => 2, text => "13:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "45th previous state" }, { col => 0, table => 2, text => "LC_PREV_STATE46" }, { col => 1, table => 2, text => "21:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "46th previous state" }, { col => 0, table => 2, text => "LC_PREV_STATE47" }, { col => 1, table => 2, text => "29:24" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "47th previous state" }, { col => undef, table => undef, text => "Link Control State Registers" }, { col => "heading", table => 3, text => "PCIE_P_CNTL - RW - 32 bits - PCIEIND:0x40", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "P_PWRDN_EN" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Enable powering down transmitter and receiver pads along ", }, { col => 3, table => 3, text => "with PLL macros", }, { col => 0, table => 3, text => "P_SYMALIGN_MODE" }, { col => 1, table => 3, text => 1 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Data Valid generation bit - iMODE = 0 (Relax Mode): ", }, { col => 3, table => 3, text => "update its symbol right away when detect ", }, { col => 3, table => 3, text => "any bit shift, i.e. data_valid will always ", }, { col => 3, table => 3, text => "assert. iMODE = 1 (Aggressive Mode): need confirmation ", }, { col => 3, table => 3, text => "before muxing out the data", }, { col => 0, table => 3, text => "P_PLL_PWRDN_IN_L1L23" }, { col => 1, table => 3, text => 3 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Enable PLL powerdown in L1 or L23 Ready states - only if ", }, { col => 3, table => 3, text => "all the associated LC's are in Sates L1 / ", }, { col => 3, table => 3, text => "L23 corresponding to 4 / 2 lanes based ", }, { col => 3, table => 3, text => "on mpConfig and architecture" }, { col => 0, table => 3, text => "P_PLL_BUF_PDNB" }, { col => 1, table => 3, text => 4 }, { col => 2, table => 3, text => "0x1" }, { col => 3, table => 3, text => "Disable 10X clock pad on a per PLL basis - should be 1'b0 ", }, { col => 3, table => 3, text => "in order to activate this powersafe feature.", }, { col => 3, table => 3, text => " 0=Enable PLL Buffer to power down during L1 ", }, { col => 3, table => 3, text => " 1=Always keep PLL Buffer running " }, { col => 0, table => 3, text => "P_TXCLK_SND_PWRDN" }, { col => 1, table => 3, text => 5 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Enable powering down TXCLK clock pads on the transmit ", }, { col => 3, table => 3, text => "side. Each clock pad corresponds to logic ", }, { col => 3, table => 3, text => "associated with 4 lanes." }, { col => 0, table => 3, text => "P_TXCLK_RCV_PWRDN" }, { col => 1, table => 3, text => 6 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Enable powering down TXCLK clock pads on the receive ", }, { col => 3, table => 3, text => "side. Each clock pad corresponds to logic ", }, { col => 3, table => 3, text => "associated with 4 lanes." }, ], }, { num => 63, text => [ { col => 0, table => 0, text => "PI_SYMALIGN_DIS_ELIDLE" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol Alignment Statemachine control signal: ", }, { col => 3, table => 0, text => "iDIS_ELIDLE = 0, ElectIdle assertion will ", }, { col => 3, table => 0, text => "be effective in state machine ", }, { col => 3, table => 0, text => "re-initialization. iDIS_ELIDLE = 1, ElectIdle will be ", }, { col => 3, table => 0, text => "ineffective in state machine ", }, { col => 3, table => 0, text => "re-initialization" }, { col => 0, table => 0, text => "P_MASK_RCVR_EIDLE_EN" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable EIDLE mask for powered down receivers.", }, { col => 3, table => 0, text => " 0=dont intercept ELEC_IDLE in power down ", }, { col => 3, table => 0, text => " 1=intercept ELEC_IDLE in RX power down ", }, { col => 0, table => 0, text => "P_PLL_PDNB" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Enable PLL only (not the buffer) to power down in L1 or ", }, { col => 3, table => 0, text => "L23ready states." }, { col => 3, table => 0, text => " 0=Enable PLL to power down during L1 ", }, { col => 3, table => 0, text => " 1=Always keep PLL running " }, { col => 0, table => 0, text => "P_EBUF_SYNC_MODE" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=double flops " }, { col => 3, table => 0, text => " 1=single flop " }, { col => 0, table => 0, text => "P_LDSK_MASK_RCVR_ELEC_IDLE" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=GEN1:not mask-off GEN2: mask-off " }, { col => 3, table => 0, text => " 1=mask-off for GEN1 and GEN2 " }, { col => 0, table => 0, text => "P_ALLOW_PRX_FRONTEND_SHUTOFF" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable PHY's RX FRONTEND to shut off during L1 when ", }, { col => 3, table => 0, text => "PLL power down is enabled." }, { col => 3, table => 0, text => " 0=RX Frontend is always power on " }, { col => 3, table => 0, text => " 1=RX Frontend is shutoff during L1 when PLL power ", }, { col => 3, table => 0, text => "down is enabled " }, { col => 0, table => 0, text => "P_ALWAYS_USE_FAST_TXCLK" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Bypass TXCLK_SWITCH and use 500MHz TXCLK from ", }, { col => 3, table => 0, text => "PLL for both GEN1 and GEN2 speed." }, { col => 3, table => 0, text => " 0=TXCLK will be either 250MHz or 500MHz depends on ", }, { col => 3, table => 0, text => "port speeds " }, { col => 3, table => 0, text => " 1=Bypass TXCLK_SWITCH and always use 500MHz ", }, { col => 3, table => 0, text => "TXCLK " }, { col => 0, table => 0, text => "P_ELEC_IDLE_MODE" }, { col => 1, table => 0, text => "15:14" }, { col => 2, table => 0, text => "0x0Electrical Idle Mode for PI (Physical Layer).", }, { col => 3, table => 0, text => " 0=GEN1 - entry:PHY, exit:PHY ; GEN2 - entry:infer, ", }, { col => 3, table => 0, text => "exit:PHY " }, { col => 3, table => 0, text => " 1=GEN1 - entry:infer, exit:PHY; GEN2 - entry:infer, exit ", }, { col => 3, table => 0, text => "PHY " }, { col => 3, table => 0, text => " 2=GEN1 - entry:PHY, exit:PHY ; GEN2 - entry:PHY, ", }, { col => 3, table => 0, text => "exit:PHY " }, { col => 3, table => 0, text => " 3=Reserved " }, { col => 0, table => 0, text => "RXP_XBAR_MUX0" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Data routing cross bar mux - default 1'b0", }, { col => 0, table => 0, text => "RXP_XBAR_MUX1" }, { col => 1, table => 0, text => "19:18" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Data routing cross bar mux - default 1'b1", }, { col => 0, table => 0, text => "RXP_XBAR_MUX2" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => "Data routing cross bar mux - default 1'b2", }, { col => 0, table => 0, text => "RXP_XBAR_MUX3" }, { col => 1, table => 0, text => "23:22" }, { col => 2, table => 0, text => "0x3" }, { col => 3, table => 0, text => "Data routing cross bar mux - default 1'b3", }, { col => 0, table => 0, text => "PI_RXEN_GATER" }, { col => 1, table => 0, text => "27:24" }, { col => 2, table => 0, text => "0x2" }, { col => 0, table => 0, text => "RXP_REALIGN_ON_EACH_TSX_OR_S" }, { col => 0, table => 0, text => "KP" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=LDSK only taking deskew on deskewing error detect ", }, { col => 3, table => 0, text => " 1=taking deskew on every TSX and SKP OS ", }, { col => 0, table => 0, text => "LC_RXP_DONT_ALIGN_ON_TSx" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Control Lane Deskew TS detection in L1 and L23", }, { col => 3, table => 0, text => " 0=Don't mask out TS ordered sets during L1 and L23. ", }, { col => 3, table => 0, text => " 1=Mask out lane deskew TSx detection during L1 and ", }, { col => undef, table => undef, text => "L23. " }, { col => undef, table => undef, text => "PHY Control Register" }, { col => undef, table => undef, text => "PCIE_P_BUF_STATUS - RW - 32 bits - PCIEIND:0x41", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "P_ELASTIC_BUF_OVERFLOW_0" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "P_ELASTIC_BUF_OVERFLOW_1" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "P_ELASTIC_BUF_OVERFLOW_2" }, { col => undef, table => undef, text => 2 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => undef, table => undef, text => 2 }, ], }, { num => 64, text => [ { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_3" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 3 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_4" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 4 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_5" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 5 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_6" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 6 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_7" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 7 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_8" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 8 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_9" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 9 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_10" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 10 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_11" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 11 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_12" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 12 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_13" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 13 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_14" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 14 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_15" }, { col => 1, table => 0, text => 15 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 15 }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_0" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 0", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_1" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 1", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_2" }, { col => 1, table => 0, text => 18 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 2", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_3" }, { col => 1, table => 0, text => 19 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 3", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_4" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 4", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_5" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 5", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_6" }, { col => 1, table => 0, text => 22 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 6", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_7" }, { col => 1, table => 0, text => 23 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 7", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_8" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 8", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_9" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 9", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_10" }, { col => 1, table => 0, text => 26 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 10", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_11" }, { col => 1, table => 0, text => 27 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 11", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_12" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 12", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_13" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 13", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_14" }, { col => 1, table => 0, text => 30 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 14", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_15" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Symbol skew buffer over/underflow: lane 15", }, { col => undef, table => undef, text => "PHY BUFFER STATUS REGISTER" }, { col => undef, table => undef, text => "PCIE_P_DECODER_STATUS - RW - 32 bits - PCIEIND:0x42", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "P_DECODE_ERR_0" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Indicates which lane has the decoding error, i.e. Can't ", }, { col => undef, table => undef, text => "decode the incoming data. bit15 => Lane ", }, { col => undef, table => undef, text => "15 (0 = OK, 1 = error), etc" }, { col => undef, table => undef, text => "P_DECODE_ERR_1" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Indicates which lane has the decoding error, i.e. Can't ", }, { col => undef, table => undef, text => "decode the incoming data. bit15 => Lane ", }, { col => undef, table => undef, text => "15 (0 = OK, 1 = error), etc" }, { col => undef, table => undef, text => "P_DECODE_ERR_2" }, { col => undef, table => undef, text => 2 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Indicates which lane has the decoding error, i.e. Can't ", }, { col => undef, table => undef, text => "decode the incoming data. bit15 => Lane ", }, { col => undef, table => undef, text => "15 (0 = OK, 1 = error), etc" }, { col => undef, table => undef, text => "P_DECODE_ERR_3" }, { col => undef, table => undef, text => 3 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Indicates which lane has the decoding error, i.e. Can't ", }, { col => undef, table => undef, text => "decode the incoming data. bit15 => Lane ", }, { col => undef, table => undef, text => "15 (0 = OK, 1 = error), etc" }, ], }, { num => 66, text => [ { col => undef, table => undef, text => "P_DISPARITY_ERR_13" }, { col => undef, table => undef, text => 29 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Indicates which lane has the link error: bit15 => Lane 15 (0 ", }, { col => undef, table => undef, text => "= OK, 1 = error), etc" }, { col => undef, table => undef, text => "P_DISPARITY_ERR_14" }, { col => undef, table => undef, text => 30 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Indicates which lane has the link error: bit15 => Lane 15 (0 ", }, { col => undef, table => undef, text => "= OK, 1 = error), etc" }, { col => undef, table => undef, text => "P_DISPARITY_ERR_15" }, { col => undef, table => undef, text => 31 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Indicates which lane has the link error: bit15 => Lane 15 (0 ", }, { col => undef, table => undef, text => "= OK, 1 = error), etc" }, { col => undef, table => undef, text => "PHY DECODER STATUS REGISTER" }, { col => "heading", table => 0, text => "PCIE_P_MISC_DEBUG_STATUS - RW - 32 bits - PCIEIND:0x43", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "P_LANE_REVERSAL (R)" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Lane Reversal" }, { col => 3, table => 0, text => " 0=All lane order is normal " }, { col => 3, table => 0, text => " 1=All lane order is reversed " }, { col => 0, table => 0, text => "P_HW_DEBUG" }, { col => 1, table => 0, text => "15:4" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "P_INSERT_ERROR_0" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 0", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane0 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_1" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 1", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane1 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_2" }, { col => 1, table => 0, text => 18 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 2", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane2 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_3" }, { col => 1, table => 0, text => 19 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 3", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane3 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_4" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 4", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane4 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_5" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 5", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane5 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_6" }, { col => 1, table => 0, text => 22 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 6", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane6 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_7" }, { col => 1, table => 0, text => 23 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 7", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane7 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_8" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 8", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane8 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_9" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 9", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane9 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_10" }, { col => 1, table => 0, text => 26 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 10", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane10 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, ], }, { num => 67, text => [ { col => undef, table => undef, text => "P_INSERT_ERROR_11" }, { col => undef, table => undef, text => 27 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Transmit invalid symbol 10'b0001111001 on lane 11", }, { col => undef, table => undef, text => " 0=Normal Operation " }, { col => undef, table => undef, text => " 1=Inserting error on Transmitting Lane11 by replacing one ", }, { col => undef, table => undef, text => "symbol with an invalid symbol " }, { col => undef, table => undef, text => "P_INSERT_ERROR_12" }, { col => undef, table => undef, text => 28 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Transmit invalid symbol 10'b0001111001 on lane 12", }, { col => undef, table => undef, text => " 0=Normal Operation " }, { col => undef, table => undef, text => " 1=Inserting error on Transmitting Lane12 by replacing one ", }, { col => undef, table => undef, text => "symbol with an invalid symbol " }, { col => undef, table => undef, text => "P_INSERT_ERROR_13" }, { col => undef, table => undef, text => 29 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Transmit invalid symbol 10'b0001111001 on lane 13", }, { col => undef, table => undef, text => " 0=Normal Operation " }, { col => undef, table => undef, text => " 1=Inserting error on Transmitting Lane13 by replacing one ", }, { col => undef, table => undef, text => "symbol with an invalid symbol " }, { col => undef, table => undef, text => "P_INSERT_ERROR_14" }, { col => undef, table => undef, text => 30 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Transmit invalid symbol 10'b0001111001 on lane 14", }, { col => undef, table => undef, text => " 0=Normal Operation " }, { col => undef, table => undef, text => " 1=Inserting error on Transmitting Lane14 by replacing one ", }, { col => undef, table => undef, text => "symbol with an invalid symbol " }, { col => undef, table => undef, text => "P_INSERT_ERROR_15" }, { col => undef, table => undef, text => 31 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Transmit invalid symbol 10'b0001111001 on lane 15", }, { col => undef, table => undef, text => " 0=Normal Operation " }, { col => undef, table => undef, text => " 1=Inserting error on Transmitting Lane15 by replacing one ", }, { col => undef, table => undef, text => "symbol with an invalid symbol " }, { col => undef, table => undef, text => "PHY MISCELLANEOUS DEBUG STATUS REGISTER", }, { col => "heading", table => 1, text => "PCIE_P_SYMSYNC_CTL - RW - 32 bits - PCIEIND:0x46", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "P_SYMSYNC_ELECT_IDLE_DET_EN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Use Electrical Idle Detect to filter out garbage data", }, { col => 0, table => 1, text => "P_SYMSYNC_SYNC_MODE" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "SYMSYNC synchronous mode - 1 look for iMGood ", }, { col => 3, table => 1, text => "consecutive good COMMAs, 0 look for iMGood consecutive ", }, { col => 3, table => 1, text => "good symbols" }, { col => 0, table => 1, text => "P_SYMSYNC_M_GOOD" }, { col => 1, table => 1, text => "9:2" }, { col => 2, table => 1, text => "0x7" }, { col => 3, table => 1, text => "M parameter of Good symbols or Commas (should be ", }, { col => 3, table => 1, text => "greater than two)" }, { col => 0, table => 1, text => "P_SYMSYNC_N_BAD" }, { col => 1, table => 1, text => "17:10" }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "N parameter of Bad symbols (can be 1 or more)", }, { col => 0, table => 1, text => "P_SYMSYNC_PAD_MODE" }, { col => 1, table => 1, text => "19:18" }, { col => 2, table => 1, text => "0x3" }, { col => 3, table => 1, text => "Mode select of Good known symbols for replacement of the ", }, { col => 3, table => 1, text => "Bad symbols" }, { col => 0, table => 1, text => "P_SYMSYNC_BYPASS_MODE" }, { col => 1, table => 1, text => 20 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Bypass mode - 1 just let data and DValid flow through", }, { col => 3, table => 1, text => " 0=Bypass Symsync and Disable Symsync ", }, { col => 3, table => 1, text => " 1=Enable Symsync " }, { col => 0, table => 1, text => "P_SYMSYNC_ENABLE_IN_GEN1" }, { col => 1, table => 1, text => 21 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable Symsync for GEN1" }, { col => 3, table => 1, text => " 0=SYMSYNC is enabled for GEN2 only " }, { col => undef, table => undef, text => " 1=Enable Symsync for GEN1 as well ", }, { col => undef, table => undef, text => "SYMSYNC Control Registers" }, { col => undef, table => undef, text => "PCIE_P_IMP_CNTL_STRENGTH - RW - 32 bits - PCIEIND:0x60", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "P_TX_STR_CNTL_READ_BACK (R)" }, { col => undef, table => undef, text => "3:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Store the readback value of current controller", }, { col => undef, table => undef, text => "P_TX_IMP_CNTL_READ_BACK (R)" }, { col => undef, table => undef, text => "7:4" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Store the readback value of TX impedance controller", }, { col => undef, table => undef, text => "P_RX_IMP_CNTL_READ_BACK (R)" }, { col => undef, table => undef, text => "11:8" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Store the readback value of RX impedance controller", }, { col => undef, table => undef, text => "P_TX_STR_CNTL" }, { col => undef, table => undef, text => "19:16" }, { col => undef, table => undef, text => "0x7" }, { col => undef, table => undef, text => "Set the initial default current strength to 4'b0111", }, { col => undef, table => undef, text => "P_TX_IMP_CNTL" }, { col => undef, table => undef, text => "23:20" }, { col => undef, table => undef, text => "0x6" }, { col => undef, table => undef, text => "Default TX impedance control value", }, { col => undef, table => undef, text => "P_RX_IMP_CNTL" }, { col => undef, table => undef, text => "27:24" }, { col => undef, table => undef, text => "0x6" }, { col => undef, table => undef, text => "Default RX impedance control value", }, { col => undef, table => undef, text => "PI_HALT_IMP_CAL" }, { col => undef, table => undef, text => 28 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "P_PAD_MANUAL_OVERRIDE" }, { col => undef, table => undef, text => 31 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Enable Current and Impedance control values to override", }, { col => undef, table => undef, text => " 0=Allow normal impedance compensation operation ", }, { col => undef, table => undef, text => " 1=Default to manual settings ", }, ], }, { num => 68, text => [ { col => undef, table => undef, text => "PHY IMPEDANCE CONTROL STRENGTH REGISTER", }, { col => "heading", table => 0, text => "PCIE_P_IMP_CNTL_UPDATE - RW - 32 bits - PCIEIND:0x61", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "P_IMP_PAD_UPDATE_RATE" }, { col => 1, table => 0, text => "4:0" }, { col => 2, table => 0, text => "0xe" }, { col => 3, table => 0, text => "PAD's update interval" }, { col => 3, table => 0, text => " 0=PHY130 default 0xf " }, { col => 3, table => 0, text => " 1=PHY90 default 0xe " }, { col => 0, table => 0, text => "P_IMP_PAD_SAMPLE_DELAY" }, { col => 1, table => 0, text => "12:8" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Sampling window" }, { col => 0, table => 0, text => "P_IMP_PAD_INC_THRESHOLD" }, { col => 1, table => 0, text => "20:16" }, { col => 2, table => 0, text => "0x18" }, { col => 3, table => 0, text => "Incremental resolution" }, { col => 0, table => 0, text => "P_IMP_PAD_DEC_THRESHOLD" }, { col => 1, table => 0, text => "28:24" }, { col => 2, table => 0, text => "0x8" }, { col => undef, table => undef, text => "Decremental resolution" }, { col => undef, table => undef, text => "Impedance PAD defaults" }, { col => "heading", table => 1, text => "PCIE_P_STR_CNTL_UPDATE - RW - 32 bits - PCIEIND:0x62", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "P_STR_PAD_UPDATE_RATE" }, { col => 1, table => 1, text => "4:0" }, { col => 2, table => 1, text => "0xf" }, { col => 3, table => 1, text => "PAD's update interval" }, { col => 3, table => 1, text => " 0=PHY130 default 0xf " }, { col => 3, table => 1, text => " 1=PHY90 default 0xe " }, { col => 0, table => 1, text => "P_STR_PAD_SAMPLE_DELAY" }, { col => 1, table => 1, text => "12:8" }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Sampling window" }, { col => 0, table => 1, text => "P_STR_PAD_INC_THRESHOLD" }, { col => 1, table => 1, text => "20:16" }, { col => 2, table => 1, text => "0x18" }, { col => 3, table => 1, text => "Incremental resolution" }, { col => 0, table => 1, text => "P_STR_PAD_DEC_THRESHOLD" }, { col => 1, table => 1, text => "28:24" }, { col => 2, table => 1, text => "0x8" }, { col => undef, table => undef, text => "Decremental resolution" }, { col => undef, table => undef, text => "Current PAD defaults" }, { col => "heading", table => 2, text => "PCIE_P_PAD_MISC_CNTL - RW - 32 bits - PCIEIND:0x63", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "P_PAD_I_DUMMYOUT (R)" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Input from analog - 0 if PMOS cur is stronger", }, { col => 0, table => 2, text => "P_PAD_IMP_DUMMYOUT (R)" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Input from analog - 0 if PMOS imp is stronger", }, { col => 0, table => 2, text => "P_PAD_IMP_TESTOUT (R)" }, { col => 1, table => 2, text => 2 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Input from analog - 1 if NMOS imp is stronger", }, { col => 0, table => 2, text => "P_LINK_RETRAIN_ON_ERR_EN" }, { col => 1, table => 2, text => 3 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Disable error counts in LaneDeskew if Symbol unlocking, ", }, { col => 3, table => 2, text => "Code Errors or Deskew Errors are detected", }, { col => 0, table => 2, text => "P_PLLCAL_INC_LOWER_PHASE" }, { col => 1, table => 2, text => "6:4" }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0=0us " }, { col => 3, table => 2, text => " 1=1us " }, { col => 3, table => 2, text => " 2=2us " }, { col => 3, table => 2, text => " 3=4us " }, { col => 3, table => 2, text => " 4=8us " }, { col => 3, table => 2, text => " 5=12us " }, { col => 3, table => 2, text => " 6=16us " }, { col => undef, table => undef, text => " 7=24us " }, { col => undef, table => undef, text => "Pad Miscellaneous Control Registers", }, { col => undef, table => undef, text => "PCIE_P_DECODE_ERR_CNTL - RW - 32 bits - PCIEIND:0xEF", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "CODE_ERR_CNT_RESET" }, { col => undef, table => undef, text => "15:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "DISPARITY_ERR_CNT_RESET" }, { col => undef, table => undef, text => "31:16" }, { col => undef, table => undef, text => "0x0" }, ], }, { num => 69, text => [ { col => "heading", table => 0, text => "PCIE_P_DECODE_ERR_CNT_0 - R - 32 bits - PCIEIND:0xF0", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "CODE_ERR_CNT_0" }, { col => 1, table => 0, text => "15:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DISPARITY_ERR_CNT_0" }, { col => 1, table => 0, text => "31:16" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "PCIE_P_DECODE_ERR_CNT_1 - R - 32 bits - PCIEIND:0xF1", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CODE_ERR_CNT_1" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DISPARITY_ERR_CNT_1" }, { col => 1, table => 1, text => "31:16" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "PCIE_P_DECODE_ERR_CNT_2 - R - 32 bits - PCIEIND:0xF2", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "CODE_ERR_CNT_2" }, { col => 1, table => 2, text => "15:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DISPARITY_ERR_CNT_2" }, { col => 1, table => 2, text => "31:16" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "PCIE_P_DECODE_ERR_CNT_3 - R - 32 bits - PCIEIND:0xF3", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "CODE_ERR_CNT_3" }, { col => 1, table => 3, text => "15:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DISPARITY_ERR_CNT_3" }, { col => 1, table => 3, text => "31:16" }, { col => 2, table => 3, text => "0x0" }, { col => "heading", table => 4, text => "PCIE_P_DECODE_ERR_CNT_4 - R - 32 bits - PCIEIND:0xF4", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "CODE_ERR_CNT_4" }, { col => 1, table => 4, text => "15:0" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "DISPARITY_ERR_CNT_4" }, { col => 1, table => 4, text => "31:16" }, { col => 2, table => 4, text => "0x0" }, { col => "heading", table => 5, text => "PCIE_P_DECODE_ERR_CNT_5 - R - 32 bits - PCIEIND:0xF5", }, { col => 0, table => 5, text => "Field Name" }, { col => 1, table => 5, text => "Bits" }, { col => 2, table => 5, text => "Default" }, { col => 3, table => 5, text => "Description" }, ], }, { num => 70, text => [ { col => 0, table => 0, text => "CODE_ERR_CNT_5" }, { col => 1, table => 0, text => "15:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DISPARITY_ERR_CNT_5" }, { col => 1, table => 0, text => "31:16" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "PCIE_P_DECODE_ERR_CNT_6 - R - 32 bits - PCIEIND:0xF6", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CODE_ERR_CNT_6" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DISPARITY_ERR_CNT_6" }, { col => 1, table => 1, text => "31:16" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "PCIE_P_DECODE_ERR_CNT_7 - R - 32 bits - PCIEIND:0xF7", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "CODE_ERR_CNT_7" }, { col => 1, table => 2, text => "15:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DISPARITY_ERR_CNT_7" }, { col => 1, table => 2, text => "31:16" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "PCIE_P_DECODE_ERR_CNT_8 - R - 32 bits - PCIEIND:0xF8", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "CODE_ERR_CNT_8" }, { col => 1, table => 3, text => "15:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DISPARITY_ERR_CNT_8" }, { col => 1, table => 3, text => "31:16" }, { col => 2, table => 3, text => "0x0" }, { col => "heading", table => 4, text => "PCIE_P_DECODE_ERR_CNT_9 - R - 32 bits - PCIEIND:0xF9", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "CODE_ERR_CNT_9" }, { col => 1, table => 4, text => "15:0" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "DISPARITY_ERR_CNT_9" }, { col => 1, table => 4, text => "31:16" }, { col => 2, table => 4, text => "0x0" }, { col => "heading", table => 5, text => "PCIE_P_DECODE_ERR_CNT_10 - R - 32 bits - PCIEIND:0xFA", }, { col => 0, table => 5, text => "Field Name" }, { col => 1, table => 5, text => "Bits" }, { col => 2, table => 5, text => "Default" }, { col => 3, table => 5, text => "Description" }, { col => 0, table => 5, text => "CODE_ERR_CNT_10" }, { col => 1, table => 5, text => "15:0" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "DISPARITY_ERR_CNT_10" }, { col => 1, table => 5, text => "31:16" }, { col => 2, table => 5, text => "0x0" }, { col => undef, table => undef, text => "PCIE_P_DECODE_ERR_CNT_11 - R - 32 bits - PCIEIND:0xFB", }, ], }, { num => 71, text => [ { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "CODE_ERR_CNT_11" }, { col => 1, table => 0, text => "15:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DISPARITY_ERR_CNT_11" }, { col => 1, table => 0, text => "31:16" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "PCIE_P_DECODE_ERR_CNT_12 - R - 32 bits - PCIEIND:0xFC", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CODE_ERR_CNT_12" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DISPARITY_ERR_CNT_12" }, { col => 1, table => 1, text => "31:16" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "PCIE_P_DECODE_ERR_CNT_13 - R - 32 bits - PCIEIND:0xFD", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "CODE_ERR_CNT_13" }, { col => 1, table => 2, text => "15:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DISPARITY_ERR_CNT_13" }, { col => 1, table => 2, text => "31:16" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "PCIE_P_DECODE_ERR_CNT_14 - R - 32 bits - PCIEIND:0xFE", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "CODE_ERR_CNT_14" }, { col => 1, table => 3, text => "15:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DISPARITY_ERR_CNT_14" }, { col => 1, table => 3, text => "31:16" }, { col => 2, table => 3, text => "0x0" }, { col => "heading", table => 4, text => "PCIE_P_DECODE_ERR_CNT_15 - R - 32 bits - PCIEIND:0xFF", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "CODE_ERR_CNT_15" }, { col => 1, table => 4, text => "15:0" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "DISPARITY_ERR_CNT_15" }, { col => 1, table => 4, text => "31:16" }, { col => 2, table => 4, text => "0x0" }, { col => undef, table => undef, text => "PCIE_TX_CNTL - RW - 32 bits - PCIEIND_P:0x20", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "TX_REPLAY_NUM_COUNT (R)" }, { col => undef, table => undef, text => "9:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "TX Replay Number Counter - counter to keep track of the ", }, { col => undef, table => undef, text => "number of replays that have occured", }, { col => undef, table => undef, text => "TX_SNR_OVERRIDE" }, { col => undef, table => undef, text => "11:10" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Snoop Not Required Override - control of the Snoop bit for ", }, { col => undef, table => undef, text => "master requests" }, { col => undef, table => undef, text => " 0=Generate bit as normal " }, { col => undef, table => undef, text => " 1=Override equation, and always set bit ", }, { col => undef, table => undef, text => " 2=Override equation, and always clear bit ", }, { col => undef, table => undef, text => " 3=Invalid " }, ], }, { num => 72, text => [ { col => 0, table => 0, text => "TX_RO_OVERRIDE" }, { col => 1, table => 0, text => "13:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Relaxed Ordering Override - control relaxed ordering bit for ", }, { col => 3, table => 0, text => "master requests" }, { col => 3, table => 0, text => " 0=Generate bit as normal " }, { col => 3, table => 0, text => " 1=Override equation, and always set bit ", }, { col => 3, table => 0, text => " 2=Override equation, and always clear bit ", }, { col => 3, table => 0, text => " 3=Invalid " }, { col => 0, table => 0, text => "TX_PACK_PACKET_DIS" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Packet Packing Disable - back-to-back packing of TLP and ", }, { col => 3, table => 0, text => "DLLP" }, { col => 3, table => 0, text => " 0=Place packets as close as allowable ", }, { col => 3, table => 0, text => " 1=Place STP/SDP in lane 0 only " }, { col => 0, table => 0, text => "TX_GENERATE_CRC_ERR" }, { col => 1, table => 0, text => 15 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Generate CRC errors from TX by zeroing CRC field.", }, { col => 3, table => 0, text => " 0=Generate proper CRC " }, { col => 3, table => 0, text => " 1=Generate bad CRC " }, { col => 0, table => 0, text => "TX_GAP_BTW_PKTS" }, { col => 1, table => 0, text => "18:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Number of idle cycles between DLLP and TLP", }, { col => 0, table => 0, text => "TX_FLUSH_TLP_DIS" }, { col => 1, table => 0, text => 19 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Disable flushing TLPs when Data Link is down", }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Disable " }, { col => 0, table => 0, text => "TX_CPL_PASS_P" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Ordering rule: Let Completion Pass Posted", }, { col => 3, table => 0, text => " 0=no pass " }, { col => 3, table => 0, text => " 1=CPL pass " }, { col => 0, table => 0, text => "TX_NP_PASS_P" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Ordering rule: Let Non-Posted Pass Posted", }, { col => 3, table => 0, text => " 0=no pass " }, { col => 3, table => 0, text => " 1=NP pass " }, { col => 0, table => 0, text => "TX_FC_UPDATE_TIMEOUT_SEL" }, { col => 1, table => 0, text => "25:24" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => "To adjust the length of the timeout interval before sending ", }, { col => 3, table => 0, text => "out flow control update" }, { col => 3, table => 0, text => " 0=Disable flow control " }, { col => 3, table => 0, text => " 1=4x clock cycle " }, { col => 3, table => 0, text => " 2=1024x clock cycle " }, { col => 3, table => 0, text => " 3=4096x clock cycle " }, { col => 0, table => 0, text => "TX_FC_UPDATE_TIMEOUT" }, { col => 1, table => 0, text => "31:26" }, { col => 2, table => 0, text => "0x7" }, { col => undef, table => undef, text => "Interval length to send flow control update", }, { col => undef, table => undef, text => "TX Control Register" }, { col => "heading", table => 1, text => "PCIE_TX_SEQ - R - 32 bits - PCIEIND_P:0x24", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TX_NEXT_TRANSMIT_SEQ" }, { col => 1, table => 1, text => "11:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Next Transmit Sequence Number to send out", }, { col => 0, table => 1, text => "TX_ACKD_SEQ" }, { col => 1, table => 1, text => "27:16" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Last Acknowledged Sequence Number", }, { col => undef, table => undef, text => "TX Sequence Register" }, { col => "heading", table => 2, text => "PCIE_TX_REPLAY - RW - 32 bits - PCIEIND_P:0x25", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "TX_REPLAY_NUM" }, { col => 1, table => 2, text => "9:0" }, { col => 2, table => 2, text => "0x3" }, { col => 3, table => 2, text => "Register to control Replay Number before Link goes to ", }, { col => 3, table => 2, text => "Retrain" }, { col => 0, table => 2, text => "TX_REPLAY_TIMER_OVERWRITE" }, { col => 1, table => 2, text => 15 }, { col => 2, table => 2, text => "0x0Trigger for Replay Timer" }, { col => 0, table => 2, text => "TX_REPLAY_TIMER" }, { col => 1, table => 2, text => "31:16" }, { col => 2, table => 2, text => "0x90" }, { col => undef, table => undef, text => "Replay Timer - when expired do Replay", }, { col => undef, table => undef, text => "TX Replay Register" }, { col => "heading", table => 3, text => "PCIE_ERR_CNTL - RW - 32 bits - PCIEIND_P:0x6A", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "ERR_REPORTING_DIS" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Disable PCI Express Advanced Error Reporting", }, ], }, { num => 73, text => [ { col => 0, table => 0, text => "ERR_GEN_INTERRUPT" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable Interrupt Generation for errors" }, { col => 0, table => 0, text => "SYM_UNLOCKED_EN" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable Reporting of Symbol Unlocked Errors", }, { col => 3, table => 0, text => " 0=disable reporting unlocked symbol errors ", }, { col => undef, table => undef, text => " 1=report unlocked symbol errors ", }, { col => undef, table => undef, text => "Error Control Registers" }, { col => "heading", table => 1, text => "PCIE_RX_CNTL - RW - 32 bits - PCIEIND_P:0x70", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "RX_IGNORE_IO_ERR" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed I/O TLP Errors" }, { col => 0, table => 1, text => "RX_IGNORE_BE_ERR" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed Byte Enable TLP Errors" }, { col => 0, table => 1, text => "RX_IGNORE_MSG_ERR" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed Message Error" }, { col => 0, table => 1, text => "RX_IGNORE_CRC_ERR (R)" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore CRC Errors" }, { col => 0, table => 1, text => "RX_IGNORE_CFG_ERR" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed Configuration Errors" }, { col => 0, table => 1, text => "RX_IGNORE_CPL_ERR" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed Completion Errors" }, { col => 0, table => 1, text => "RX_IGNORE_EP_ERR" }, { col => 1, table => 1, text => 6 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed EP Errors" }, { col => 0, table => 1, text => "RX_IGNORE_LEN_MISMATCH_ERR" }, { col => 1, table => 1, text => 7 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed Length Mismatch Errors" }, { col => 0, table => 1, text => "RX_IGNORE_MAX_PAYLOAD_ERR" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed Maximum Payload Errors" }, { col => 0, table => 1, text => "RX_IGNORE_TC_ERR" }, { col => 1, table => 1, text => 9 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed Traffic Class Errors" }, { col => 0, table => 1, text => "RX_IGNORE_CFG_UR" }, { col => 1, table => 1, text => 10 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "RESERVED" }, { col => 0, table => 1, text => "RX_IGNORE_IO_UR" }, { col => 1, table => 1, text => 11 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "RESERVED" }, { col => 0, table => 1, text => "RX_IGNORE_VEND0_UR" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Vendor Type 0 Messages" }, { col => 0, table => 1, text => "RX_NAK_IF_FIFO_FULL" }, { col => 1, table => 1, text => 13 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Send NAK if RX internal FIFO is full" }, { col => 0, table => 1, text => "RX_GEN_ONE_NAK" }, { col => 1, table => 1, text => 14 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Generate NAK only for the first bad packet until replayed", }, { col => 0, table => 1, text => "RX_FC_INIT_FROM_REG" }, { col => 1, table => 1, text => 15 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Flow Control Initialization from registers", }, { col => 3, table => 1, text => " 0=Init FC from FIFO sizes " }, { col => 3, table => 1, text => " 1=Init FC from registers " }, { col => 0, table => 1, text => "RX_RCB_CPL_TIMEOUT" }, { col => 1, table => 1, text => "18:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "RCB cpl timeout" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=50us " }, { col => 3, table => 1, text => " 2=2.5ms " }, { col => 3, table => 1, text => " 3=6.25ms " }, { col => 3, table => 1, text => " 4=12.5ms " }, { col => 3, table => 1, text => " 5=25ms " }, { col => 3, table => 1, text => " 6=125ms " }, { col => 3, table => 1, text => " 7=0.25ms " }, { col => 0, table => 1, text => "RX_RCB_CPL_TIMEOUT_MODE" }, { col => 1, table => 1, text => 19 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "RCB cpl timeout on link down" }, { col => 0, table => 1, text => "RX_PCIE_CPL_TIMEOUT_DIS" }, { col => 1, table => 1, text => 20 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "RX Control Register" }, { col => "heading", table => 2, text => "PCIE_RX_CREDITS_ALLOCATED_P - R - 32 bits - PCIEIND_P:0x80", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "RX_CREDITS_ALLOCATED_PD" }, { col => 1, table => 2, text => "11:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "For posted TLP data, t h e n u m b e r o f F C u n i t s g r a n t e d ", }, { col => 3, table => 2, text => "to transmitter since initialization, modulo 4096", }, { col => 0, table => 2, text => "RX_CREDITS_ALLOCATED_PH" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "For posted TLP header, the number of FC units granted ", }, { col => undef, table => undef, text => "to transmitter since initialization, modulo 256", }, { col => undef, table => undef, text => "RX Credits Allocated Register (Posted)", }, { col => "heading", table => 3, text => "PCIE_RX_CREDITS_ALLOCATED_NP - R - 32 bits - PCIEIND_P:0x81", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, ], }, { num => 74, text => [ { col => 0, table => 0, text => "RX_CREDITS_ALLOCATED_NPD" }, { col => 1, table => 0, text => "11:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "For non-posted TLP data, the number of F C u n i t s g r a n t e d ", }, { col => 3, table => 0, text => "to transmitter since initialization, modulo 4096", }, { col => 0, table => 0, text => "RX_CREDITS_ALLOCATED_NPH" }, { col => 1, table => 0, text => "23:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "For non-posted TLP header, the number of FC units ", }, { col => 3, table => 0, text => "granted to transmitter since initialization, ", }, { col => undef, table => undef, text => "modulo 256" }, { col => undef, table => undef, text => "RX Credits Allocated Register (Non-Posted)", }, { col => "heading", table => 1, text => "PCIE_RX_CREDITS_ALLOCATED_CPL - R - 32 bits - PCIEIND_P:0x82", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "R X _ C R E D I T S _ A L L O C A T E D _ C P L D", }, { col => 2, table => 1, text => "1 1 : 0" }, { col => 3, table => 1, text => "0 x 0" }, { col => 3, table => 1, text => "F o r c o m p l e t i o n T L P d a t a , t h e n u m b e r o f F C u n i t s g r a n t e d ", }, { col => 3, table => 1, text => "to transmitter since initialization, modulo 4096", }, { col => 0, table => 1, text => "RX_CREDITS_ALLOCATED_CPLH" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "For completion TLP header, the number of FC units granted ", }, { col => undef, table => undef, text => "to transmitter since initialization, modulo 256", }, { col => undef, table => undef, text => "RX Credits Allocated Register (Completion)", }, { col => "heading", table => 2, text => "PCIE_RX_CREDITS_RECEIVED_P - R - 32 bits - PCIEIND_P:0x83", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "RX_CREDITS_RECEIVED_PD" }, { col => 1, table => 2, text => "11:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "For posted T L P d a t a , t h e n u m b e r o f F C u n i t s c o n s u m e d ", }, { col => 3, table => 2, text => "by valid TLP received since initialization, modulo 4096", }, { col => 0, table => 2, text => "RX_CREDITS_RECEIVED_PH" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "For posted TLP header, the number of FC units consumed ", }, { col => undef, table => undef, text => "by valid TLP received since initialization, modulo 256", }, { col => undef, table => undef, text => "RX Credits Received Register (Posted)", }, { col => "heading", table => 3, text => "PCIE_RX_CREDITS_RECEIVED_NP - R - 32 bits - PCIEIND_P:0x84", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "RX_CREDITS_RECEIVED_NPD" }, { col => 1, table => 3, text => "11:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "For non-posted TLP data, the number of FC units ", }, { col => 3, table => 3, text => "consumed by valid TLP received since ", }, { col => 3, table => 3, text => "initialization, modulo 4096" }, { col => 0, table => 3, text => "RX_CREDITS_RECEIVED_NPH" }, { col => 1, table => 3, text => "23:16" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "For non-posted TLP header, the number of FC units ", }, { col => 3, table => 3, text => "consumed by valid TLP received since ", }, { col => undef, table => undef, text => "initialization, modulo 256" }, { col => undef, table => undef, text => "RX Credits Received Register (Non-Posted)", }, { col => "heading", table => 4, text => "PCIE_RX_CREDITS_RECEIVED_CPL - R - 32 bits - PCIEIND_P:0x85", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "RX_CREDITS_RECEIVED_CPLD" }, { col => 1, table => 4, text => "11:0" }, { col => 2, table => 4, text => "0x0For completion TLP data, the number of FC units consumed ", }, { col => 3, table => 4, text => " by valid TLP received since " }, { col => 3, table => 4, text => "initialization, module 4096" }, { col => 0, table => 4, text => "RX_CREDITS_RECEIVED_CPLH" }, { col => 1, table => 4, text => "23:16" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "For completion TLP header, the number of FC units ", }, { col => 3, table => 4, text => "consumed by valid TLP received since ", }, { col => undef, table => undef, text => "initialization, module 256" }, { col => undef, table => undef, text => "RX Credits Received Register (Completion)", }, ], }, { num => 75, text => [ { col => "heading", table => 0, text => "PCIE_LC_CNTL - RW - 32 bits - PCIEIND_P:0xA0", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "LC_CM_HI_ENABLE_COUNT" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable count for CM_HIGH - when transmitter is to be ", }, { col => 3, table => 0, text => "turned on stop when the counter reaches ", }, { col => 3, table => 0, text => "CM_HI_COUNT_LIMIT_ON. If number ", }, { col => 3, table => 0, text => "o f l a n e s = 1 o r 2 : C M _ H I _ C O U N T _ L I M I T _ O N = 1 2 o r 1 0 . ", }, { col => 3, table => 0, text => "If number of lanes = 3 or 4: CM_HI_COUNT_LIMIT_ON = ", }, { col => 3, table => 0, text => "10 or 12. If number of lanes > 4: ", }, { col => 3, table => 0, text => "CM_HI_COUNT_LIMIT_ON = 10 or 15." }, { col => 0, table => 0, text => "LC_DONT_ENTER_L23_IN_D0" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Do not enter L23 in D0 state." }, { col => 0, table => 0, text => "LC_RESET_L_IDLE_COUNT_EN" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable reset of electrical idle counter.", }, { col => 0, table => 0, text => "LC_RESET_LINK" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Reset an individual link without resetting the other ports.", }, { col => 0, table => 0, text => "LC_16X_CLEAR_TX_PIPE" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x5" }, { col => 3, table => 0, text => "Adjust the time that the LC waits for the pipe to be idle. ", }, { col => 3, table => 0, text => "Setting this field to 0 results in the maximum time. ", }, { col => 3, table => 0, text => "Otherwise, the delay increases as this field is incremented.", }, { col => 0, table => 0, text => "LC_L0S_INACTIVITY" }, { col => 1, table => 0, text => "11:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "L0s inactivity timer setting" }, { col => 3, table => 0, text => " 0=L0s is disabled " }, { col => 3, table => 0, text => " 1=40ns " }, { col => 3, table => 0, text => " 2=80ns " }, { col => 3, table => 0, text => " 3=120ns " }, { col => 3, table => 0, text => " 4=200ns " }, { col => 3, table => 0, text => " 5=400ns " }, { col => 3, table => 0, text => " 6=1us " }, { col => 3, table => 0, text => " 7=2us " }, { col => 3, table => 0, text => " 8=4us " }, { col => 3, table => 0, text => " 9=10us " }, { col => 3, table => 0, text => " 10=40us " }, { col => 3, table => 0, text => " 11=100us " }, { col => 3, table => 0, text => " 12=400us " }, { col => 3, table => 0, text => " 13=1ms " }, { col => 3, table => 0, text => " 14=4ms " }, { col => 0, table => 0, text => "LC_L1_INACTIVITY" }, { col => 1, table => 0, text => "15:12" }, { col => 2, t